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https://github.com/brain-hackers/u-boot-brain
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![Mario Six](/assets/img/avatar_default.png)
Add a U-Boot specific dts file, which encapsulates the needed modifications to the Gazerbeam Linux device tree. Signed-off-by: Mario Six <mario.six@gdsys.cc>
251 lines
4.0 KiB
Plaintext
251 lines
4.0 KiB
Plaintext
#include <dt-bindings/memory/mpc83xx-sdram.h>
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#include <dt-bindings/clk/mpc83xx-clk.h>
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/ {
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aliases {
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i2c0 = &IIC;
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i2c1 = &IIC2;
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i2c2 = "/fpga0bus/fpga0_iic_main";
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i2c3 = "/fpga0bus/fpga0_iic_video0";
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i2c4 = "/fpga0bus/fpga0_iic_video1";
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i2c5 = "/fpga0bus/fpga0_iic_usb";
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gdsys_soc0 = "/fpga0bus";
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gdsys_soc1 = "/fpga1bus";
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ioep0 = "/fpga0bus/fpga0_ep0";
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ioep1 = "/fpga0bus/fpga1_ep0";
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};
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chosen {
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stdout-path = &serial1;
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};
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cpus {
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compatible = "cpu_bus";
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u-boot,dm-pre-reloc;
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PowerPC,8308@0 {
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compatible = "fsl,mpc8308";
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clocks = <&socclocks MPC83XX_CLK_CORE
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&socclocks MPC83XX_CLK_CSB>;
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u-boot,dm-pre-reloc;
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};
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};
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board {
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compatible = "gdsys,board_gazerbeam";
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csb = <&board_soc>;
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serdes = <&SERDES>;
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rxaui0 = <&RXAUI0_0>;
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rxaui1 = <&RXAUI0_1>;
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rxaui2 = <&RXAUI0_2>;
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rxaui3 = <&RXAUI0_3>;
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rxaui4 = <&RXAUI1_0>;
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rxaui5 = <&RXAUI1_1>;
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rxaui6 = <&RXAUI1_2>;
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rxaui7 = <&RXAUI1_3>;
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fpga0 = <&FPGA0>;
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fpga1 = <&FPGA1>;
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ioep0 = <&IOEP0>;
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ioep1 = <&IOEP1>;
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ver-gpios = <&PPCPCA 12 0
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&PPCPCA 13 0
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&PPCPCA 14 0
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&PPCPCA 15 0>;
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/* MC2/SC-Board */
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var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
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&GPIO_VB0 11 0>; /* VAR-CON */
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/* MC4-Board */
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var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
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&GPIO_VB1 11 0>; /* VAR-CON */
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reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
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};
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socclocks: clocks {
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compatible = "fsl,mpc8308-clk";
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#clock-cells = <1>;
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u-boot,dm-pre-reloc;
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};
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timer {
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compatible = "fsl,mpc83xx-timer";
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clocks = <&socclocks MPC83XX_CLK_CSB>;
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};
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};
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&FPGA0 {
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reset-gpios = <&PPCPCA 26 0>;
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done-gpios = <&GPIO_VB0 19 0>;
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};
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&FPGA1 {
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status = "disable";
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};
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&FPGA0BUS {
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ranges = <0x0 0xe0600000 0x00004000>;
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fpga = <&FPGA0>;
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fpga0_video0 {
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mode = "640_480_60";
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status = "disabled";
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};
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RXAUI0_0: fpga0_rxaui@fc0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0fc0 0x10>;
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};
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fpga0_iic_video0 {
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status = "disabled";
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};
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fpga0_axi_video0 {
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status = "disabled";
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};
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fpga0_video1 {
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mode = "640_480_60";
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status = "disabled";
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};
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fpga0_iic_video1 {
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status = "disabled";
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};
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fpga0_axi_video1 {
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status = "disabled";
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};
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IOEP0: fpga0_ep0 {
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};
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RXAUI0_1: fpga0_rxaui@fd0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0fd0 0x10>;
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};
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RXAUI0_2: fpga0_rxaui@fe0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0fe0 0x10>;
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};
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RXAUI0_3: fpga0_rxaui@ff0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0ff0 0x10>;
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};
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};
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&FPGA1BUS {
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ranges = <0x0 0xe0700000 0x00004000>;
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fpga = <&FPGA1>;
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status = "disable";
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fpga1_video0 {
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mode = "640_480_60";
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};
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RXAUI1_0: fpga0_rxaui@fc0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0fc0 0x10>;
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};
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fpga1_video1 {
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mode = "640_480_60";
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};
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IOEP1: fpga1_ep0 {
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};
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RXAUI1_1: fpga0_rxaui@fd0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0fd0 0x10>;
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};
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RXAUI1_2: fpga0_rxaui@fe0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0fe0 0x10>;
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};
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RXAUI1_3: fpga0_rxaui@ff0 {
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compatible = "gdsys,rxaui_ctrl";
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reg = <0x0ff0 0x10>;
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};
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};
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&board_soc {
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u-boot,dm-pre-reloc;
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clocks = <&socclocks MPC83XX_CLK_CSB>;
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memory@2000 {
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u-boot,dm-pre-reloc;
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};
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sdhc@2e000 {
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clocks = <&socclocks MPC83XX_CLK_SDHC>;
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clock-names = "per";
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};
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SERDES: serdes@e3000 {
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reg = <0xe3000 0x200>;
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compatible = "fsl,mpc83xx-serdes";
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proto = "pex";
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serdes-clk = <100>;
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vdd;
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};
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};
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&IIC {
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clocks = <&socclocks MPC83XX_CLK_I2C1>;
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PPCPCA: pca9698@20 {
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label = "ppc";
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};
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IOPCA: pca9698@22 {
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label = "io";
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};
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at97sc3205t@29 {
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u-boot,i2c-offset-len = <0>;
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};
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};
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&IIC2 {
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clocks = <&socclocks MPC83XX_CLK_I2C2>;
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GPIO_VB0: pca9698@20 {
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label = "mc2-sc";
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};
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GPIO_VB1: pca9698@22 {
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label = "mc4";
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};
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};
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&board_soc {
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u-boot,dm-pre-reloc;
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};
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&GPIO_VB0 {
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u-boot,dm-pre-reloc;
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};
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&serial0 {
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clocks = <&socclocks MPC83XX_CLK_CSB>;
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u-boot,dm-pre-reloc;
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};
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&serial1 {
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clocks = <&socclocks MPC83XX_CLK_CSB>;
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u-boot,dm-pre-reloc;
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};
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&pci0 {
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clocks = <&socclocks MPC83XX_CLK_PCIEXP1>;
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};
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