mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-03 00:33:45 +09:00
28fe4d5b30
Move the function to soc file so that we can find all the soc/board setting in soc file and use a common board file later for all rockchip SoCs. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [Fixed up header-list to not break FASTBOOT:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
59 lines
1.2 KiB
C
59 lines
1.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2017 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/bootrom.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/timer.h>
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_MMC1;
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}
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#define SGRF_DDR_CON0 0x10150000
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void board_init_f(ulong dummy)
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{
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struct udevice *dev;
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int ret;
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#ifdef CONFIG_DEBUG_UART
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug_uart_init();
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printascii("SPL Init");
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#endif
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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rockchip_timer_init();
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printf("timer init done\n");
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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printf("DRAM init failed: %d\n", ret);
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return;
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}
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/* Disable the ddr secure region setting to make it non-secure */
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rk_clrreg(SGRF_DDR_CON0, 0x4000);
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#if defined(CONFIG_SPL_ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
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back_to_bootrom(BROM_BOOT_NEXTSTAGE);
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#endif
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}
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