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https://github.com/brain-hackers/u-boot-brain
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3eb90bad65
According to the PPC reference implementation the udelay() function is responsible for resetting the watchdog timer as frequently as needed. Most other architectures do not meet that requirement, so long-running operations might result in a watchdog reset. This patch adds a generic udelay() function which takes care of resetting the watchdog before calling an architecture-specific __udelay(). Signed-off-by: Ingo van Lil <inguin@gmx.de>
136 lines
3.1 KiB
C
136 lines
3.1 KiB
C
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Marius Groeger <mgroeger@sysgo.de>
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*
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* (C) Copyright 2002
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* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
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* Alex Zuepke <azu@sysgo.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/ixp425.h>
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#ifdef CONFIG_TIMER_IRQ
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#define FREQ 66666666
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#define CLOCK_TICK_RATE (((FREQ / CONFIG_SYS_HZ & ~IXP425_OST_RELOAD_MASK) + 1) * CONFIG_SYS_HZ)
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#define LATCH ((CLOCK_TICK_RATE + CONFIG_SYS_HZ/2) / CONFIG_SYS_HZ) /* For divider */
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/*
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* When interrupts are enabled, use timer 2 for time/delay generation...
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*/
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static volatile ulong timestamp;
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static void timer_isr(void *data)
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{
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unsigned int *pTime = (unsigned int *)data;
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(*pTime)++;
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/*
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* Reset IRQ source
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*/
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*IXP425_OSST = IXP425_OSST_TIMER_2_PEND;
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}
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ulong get_timer (ulong base)
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{
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return timestamp - base;
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}
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void reset_timer (void)
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{
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timestamp = 0;
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}
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int timer_init (void)
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{
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/* install interrupt handler for timer */
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irq_install_handler(IXP425_TIMER_2_IRQ, timer_isr, (void *)×tamp);
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/* setup the Timer counter value */
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*IXP425_OSRT2 = (LATCH & ~IXP425_OST_RELOAD_MASK) | IXP425_OST_ENABLE;
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/* enable timer irq */
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*IXP425_ICMR = (1 << IXP425_TIMER_2_IRQ);
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return 0;
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}
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#else
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ulong get_timer (ulong base)
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{
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return get_timer_masked () - base;
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}
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void ixp425_udelay(unsigned long usec)
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{
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/*
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* This function has a max usec, but since it is called from udelay
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* we should not have to worry... be happy
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*/
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unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK;
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*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
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usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
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*IXP425_OSRT1 = usecs;
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while (!(*IXP425_OSST & IXP425_OSST_TIMER_1_PEND));
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}
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void __udelay (unsigned long usec)
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{
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while (usec--) ixp425_udelay(1);
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}
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static ulong reload_constant = 0xfffffff0;
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void reset_timer_masked (void)
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{
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ulong reload = reload_constant | IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE;
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*IXP425_OSST = IXP425_OSST_TIMER_1_PEND;
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*IXP425_OSRT1 = reload;
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}
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ulong get_timer_masked (void)
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{
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/*
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* Note that it is possible for this to wrap!
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* In this case we return max.
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*/
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ulong current = *IXP425_OST1;
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if (*IXP425_OSST & IXP425_OSST_TIMER_1_PEND)
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{
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return reload_constant;
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}
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return (reload_constant - current);
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}
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int timer_init(void)
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{
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return 0;
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}
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#endif
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