mirror of
https://github.com/brain-hackers/u-boot-brain
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240 lines
5.7 KiB
C
240 lines
5.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <init.h>
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#include <log.h>
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#include <ram.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include "stm32mp1_ddr.h"
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static const char *const clkname[] = {
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"ddrc1",
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"ddrc2",
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"ddrcapb",
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"ddrphycapb",
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"ddrphyc" /* LAST clock => used for get_rate() */
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};
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int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
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{
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unsigned long ddrphy_clk;
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unsigned long ddr_clk;
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struct clk clk;
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int ret;
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unsigned int idx;
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for (idx = 0; idx < ARRAY_SIZE(clkname); idx++) {
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ret = clk_get_by_name(priv->dev, clkname[idx], &clk);
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if (!ret)
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ret = clk_enable(&clk);
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if (ret) {
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printf("error for %s : %d\n", clkname[idx], ret);
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return ret;
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}
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}
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priv->clk = clk;
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ddrphy_clk = clk_get_rate(&priv->clk);
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debug("DDR: mem_speed (%d kHz), RCC %d kHz\n",
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mem_speed, (u32)(ddrphy_clk / 1000));
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/* max 10% frequency delta */
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ddr_clk = abs(ddrphy_clk - mem_speed * 1000);
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if (ddr_clk > (mem_speed * 100)) {
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pr_err("DDR expected freq %d kHz, current is %d kHz\n",
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mem_speed, (u32)(ddrphy_clk / 1000));
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return -EINVAL;
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}
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return 0;
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}
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__weak int board_stm32mp1_ddr_config_name_match(struct udevice *dev,
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const char *name)
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{
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return 0; /* Always match */
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}
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static ofnode stm32mp1_ddr_get_ofnode(struct udevice *dev)
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{
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const char *name;
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ofnode node;
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dev_for_each_subnode(node, dev) {
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name = ofnode_get_property(node, "compatible", NULL);
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if (!board_stm32mp1_ddr_config_name_match(dev, name))
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return node;
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}
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return dev_ofnode(dev);
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}
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static __maybe_unused int stm32mp1_ddr_setup(struct udevice *dev)
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{
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struct ddr_info *priv = dev_get_priv(dev);
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int ret;
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unsigned int idx;
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struct clk axidcg;
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struct stm32mp1_ddr_config config;
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ofnode node = stm32mp1_ddr_get_ofnode(dev);
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#define PARAM(x, y, z) \
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{ .name = x, \
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.offset = offsetof(struct stm32mp1_ddr_config, y), \
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.size = sizeof(config.y) / sizeof(u32), \
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.present = z, \
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}
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#define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x, NULL)
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#define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x, NULL)
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#define PHY_PARAM_OPT(x) PARAM("st,phy-"#x, p_##x, &config.p_##x##_present)
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const struct {
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const char *name; /* name in DT */
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const u32 offset; /* offset in config struct */
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const u32 size; /* size of parameters */
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bool * const present; /* presence indication for opt */
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} param[] = {
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CTL_PARAM(reg),
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CTL_PARAM(timing),
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CTL_PARAM(map),
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CTL_PARAM(perf),
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PHY_PARAM(reg),
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PHY_PARAM(timing),
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PHY_PARAM_OPT(cal)
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};
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config.info.speed = ofnode_read_u32_default(node, "st,mem-speed", 0);
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config.info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
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config.info.name = ofnode_read_string(node, "st,mem-name");
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if (!config.info.name) {
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debug("%s: no st,mem-name\n", __func__);
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return -EINVAL;
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}
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printf("RAM: %s\n", config.info.name);
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for (idx = 0; idx < ARRAY_SIZE(param); idx++) {
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ret = ofnode_read_u32_array(node, param[idx].name,
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(void *)((u32)&config +
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param[idx].offset),
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param[idx].size);
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debug("%s: %s[0x%x] = %d\n", __func__,
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param[idx].name, param[idx].size, ret);
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if (ret &&
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(ret != -FDT_ERR_NOTFOUND || !param[idx].present)) {
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pr_err("%s: Cannot read %s, error=%d\n",
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__func__, param[idx].name, ret);
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return -EINVAL;
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}
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if (param[idx].present) {
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/* save presence of optional parameters */
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*param[idx].present = true;
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if (ret == -FDT_ERR_NOTFOUND) {
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*param[idx].present = false;
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#ifdef CONFIG_STM32MP1_DDR_INTERACTIVE
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/* reset values if used later */
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memset((void *)((u32)&config +
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param[idx].offset),
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0, param[idx].size * sizeof(u32));
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#endif
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}
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}
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}
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ret = clk_get_by_name(dev, "axidcg", &axidcg);
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if (ret) {
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debug("%s: Cannot found axidcg\n", __func__);
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return -EINVAL;
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}
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clk_disable(&axidcg); /* disable clock gating during init */
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stm32mp1_ddr_init(priv, &config);
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clk_enable(&axidcg); /* enable clock gating */
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/* check size */
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debug("%s : get_ram_size(%x, %x)\n", __func__,
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(u32)priv->info.base, (u32)STM32_DDR_SIZE);
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priv->info.size = get_ram_size((long *)priv->info.base,
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STM32_DDR_SIZE);
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debug("%s : %x\n", __func__, (u32)priv->info.size);
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/* check memory access for all memory */
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if (config.info.size != priv->info.size) {
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printf("DDR invalid size : 0x%x, expected 0x%x\n",
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priv->info.size, config.info.size);
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return -EINVAL;
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}
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return 0;
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}
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static int stm32mp1_ddr_probe(struct udevice *dev)
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{
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struct ddr_info *priv = dev_get_priv(dev);
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struct regmap *map;
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int ret;
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debug("STM32MP1 DDR probe\n");
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priv->dev = dev;
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ret = regmap_init_mem(dev_ofnode(dev), &map);
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if (ret)
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return ret;
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priv->ctl = regmap_get_range(map, 0);
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priv->phy = regmap_get_range(map, 1);
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priv->rcc = STM32_RCC_BASE;
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priv->info.base = STM32_DDR_BASE;
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#if !defined(CONFIG_TFABOOT) && \
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(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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priv->info.size = 0;
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return stm32mp1_ddr_setup(dev);
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#else
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ofnode node = stm32mp1_ddr_get_ofnode(dev);
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priv->info.size = ofnode_read_u32_default(node, "st,mem-size", 0);
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return 0;
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#endif
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}
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static int stm32mp1_ddr_get_info(struct udevice *dev, struct ram_info *info)
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{
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struct ddr_info *priv = dev_get_priv(dev);
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*info = priv->info;
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return 0;
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}
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static struct ram_ops stm32mp1_ddr_ops = {
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.get_info = stm32mp1_ddr_get_info,
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};
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static const struct udevice_id stm32mp1_ddr_ids[] = {
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{ .compatible = "st,stm32mp1-ddr" },
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{ }
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};
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U_BOOT_DRIVER(ddr_stm32mp1) = {
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.name = "stm32mp1_ddr",
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.id = UCLASS_RAM,
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.of_match = stm32mp1_ddr_ids,
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.ops = &stm32mp1_ddr_ops,
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.probe = stm32mp1_ddr_probe,
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.priv_auto_alloc_size = sizeof(struct ddr_info),
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};
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