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![Chris Packham](/assets/img/avatar_default.png)
The RD_SAMPLE_DELAY field is 5 bits so it needs to be masked with 0x1f instead of 0xf. Rather than checking the read sample delay for all DDR chip selects use the values for the chip selects that are actually configured. Finally continue searching for the max_phase value even if the current read_sample is the same as the max_read_sample. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
693 lines
18 KiB
C
693 lines
18 KiB
C
/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "ddr3_init.h"
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#define VREF_INITIAL_STEP 3
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#define VREF_SECOND_STEP 1
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#define VREF_MAX_INDEX 7
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#define MAX_VALUE (1024 - 1)
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#define MIN_VALUE (-MAX_VALUE)
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#define GET_RD_SAMPLE_DELAY(data, cs) ((data >> rd_sample_mask[cs]) & 0x1f)
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u32 ck_delay = (u32)-1, ck_delay_16 = (u32)-1;
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u32 ca_delay;
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int ddr3_tip_centr_skip_min_win_check = 0;
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u8 current_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
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u8 last_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
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u16 current_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
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u16 last_valid_window[MAX_BUS_NUM][MAX_INTERFACE_NUM];
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u8 lim_vref[MAX_BUS_NUM][MAX_INTERFACE_NUM];
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u8 interface_state[MAX_INTERFACE_NUM];
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u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
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u8 vref_window_size_th = 12;
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static u8 pup_st[MAX_BUS_NUM][MAX_INTERFACE_NUM];
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static u32 rd_sample_mask[] = {
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0,
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8,
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16,
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24
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};
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#define VREF_STEP_1 0
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#define VREF_STEP_2 1
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#define VREF_CONVERGE 2
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/*
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* ODT additional timing
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*/
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int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id)
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{
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u32 cs_num = 0, max_cs = 0, max_read_sample = 0, min_read_sample = 0x1f;
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u32 data_read[MAX_INTERFACE_NUM] = { 0 };
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u32 read_sample[MAX_CS_NUM];
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u32 val;
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u32 pup_index;
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int max_phase = MIN_VALUE, current_phase;
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enum hws_access_type access_type = ACCESS_TYPE_UNICAST;
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struct hws_topology_map *tm = ddr3_get_topology_map();
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
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DUNIT_ODT_CONTROL_REG,
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0 << 8, 0x3 << 8));
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CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id,
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READ_DATA_SAMPLE_DELAY,
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data_read, MASK_ALL_BITS));
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val = data_read[if_id];
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max_cs = hws_ddr3_tip_max_cs_get();
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for (cs_num = 0; cs_num < max_cs; cs_num++) {
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read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
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/* find maximum of read_samples */
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if (read_sample[cs_num] >= max_read_sample) {
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if (read_sample[cs_num] == max_read_sample) {
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/* search for max phase */;
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} else {
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max_read_sample = read_sample[cs_num];
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max_phase = MIN_VALUE;
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}
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for (pup_index = 0;
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pup_index < tm->num_of_bus_per_interface;
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pup_index++) {
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CHECK_STATUS(ddr3_tip_bus_read
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(dev_num, if_id,
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ACCESS_TYPE_UNICAST, pup_index,
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DDR_PHY_DATA,
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RL_PHY_REG + CS_REG_VALUE(cs_num),
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&val));
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current_phase = ((int)val & 0xe0) >> 6;
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if (current_phase >= max_phase)
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max_phase = current_phase;
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}
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}
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/* find minimum */
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if (read_sample[cs_num] < min_read_sample)
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min_read_sample = read_sample[cs_num];
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}
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if (min_read_sample <= tm->interface_params[if_id].cas_l) {
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min_read_sample = (int)tm->interface_params[if_id].cas_l;
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}
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min_read_sample = min_read_sample - 1;
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max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1;
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if (max_read_sample >= 0x1f)
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max_read_sample = 0x1f;
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
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ODT_TIMING_LOW,
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((min_read_sample - 1) << 12),
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0xf << 12));
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CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id,
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ODT_TIMING_LOW,
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(max_read_sample << 16),
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0x1f << 16));
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return MV_OK;
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}
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int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4])
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{
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u32 reg_pup = RESULT_DB_PHY_REG_ADDR;
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u32 reg_data;
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u32 cs_num;
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int i;
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cs_num = 0;
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/* TBD */
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reg_pup += cs_num;
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for (i = 0; i < 4; i++) {
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CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
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ACCESS_TYPE_UNICAST, i,
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DDR_PHY_DATA, reg_pup,
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®_data));
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res[i] = (reg_data >> RESULT_DB_PHY_REG_RX_OFFSET) & 0x1f;
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}
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return 0;
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}
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/*
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* This algorithm deals with the vertical optimum from Voltage point of view
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* of the sample signal.
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* Voltage sample point can improve the Eye / window size of the bit and the
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* pup.
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* The problem is that it is tune for all DQ the same so there isn't any
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* PBS like code.
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* It is more like centralization.
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* But because we don't have The training SM support we do it a bit more
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* smart search to save time.
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*/
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int ddr3_tip_vref(u32 dev_num)
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{
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/*
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* The Vref register have non linear order. Need to check what will be
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* in future projects.
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*/
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u32 vref_map[8] = {
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1, 2, 3, 4, 5, 6, 7, 0
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};
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/* State and parameter definitions */
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u32 initial_step = VREF_INITIAL_STEP;
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/* need to be assign with minus ????? */
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u32 second_step = VREF_SECOND_STEP;
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u32 algo_run_flag = 0, currrent_vref = 0;
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u32 while_count = 0;
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u32 pup = 0, if_id = 0, num_pup = 0, rep = 0;
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u32 val = 0;
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u32 reg_addr = 0xa8;
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u32 copy_start_pattern, copy_end_pattern;
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enum hws_result *flow_result = ddr3_tip_get_result_ptr(training_stage);
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u8 res[4];
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struct hws_topology_map *tm = ddr3_get_topology_map();
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CHECK_STATUS(ddr3_tip_special_rx(dev_num));
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/* save start/end pattern */
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copy_start_pattern = start_pattern;
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copy_end_pattern = end_pattern;
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/* set vref as centralization pattern */
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start_pattern = PATTERN_VREF;
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end_pattern = PATTERN_VREF;
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/* init params */
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for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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for (pup = 0;
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pup < tm->num_of_bus_per_interface; pup++) {
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current_vref[pup][if_id] = 0;
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last_vref[pup][if_id] = 0;
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lim_vref[pup][if_id] = 0;
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current_valid_window[pup][if_id] = 0;
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last_valid_window[pup][if_id] = 0;
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if (vref_window_size[if_id][pup] >
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vref_window_size_th) {
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pup_st[pup][if_id] = VREF_CONVERGE;
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DEBUG_TRAINING_HW_ALG(
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DEBUG_LEVEL_INFO,
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("VREF config, IF[ %d ]pup[ %d ] - Vref tune not requered (%d)\n",
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if_id, pup, __LINE__));
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} else {
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pup_st[pup][if_id] = VREF_STEP_1;
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CHECK_STATUS(ddr3_tip_bus_read
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(dev_num, if_id,
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ACCESS_TYPE_UNICAST, pup,
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DDR_PHY_DATA, reg_addr, &val));
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CHECK_STATUS(ddr3_tip_bus_write
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(dev_num, ACCESS_TYPE_UNICAST,
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if_id, ACCESS_TYPE_UNICAST,
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pup, DDR_PHY_DATA, reg_addr,
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(val & (~0xf)) | vref_map[0]));
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DEBUG_TRAINING_HW_ALG(
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DEBUG_LEVEL_INFO,
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("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
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if_id, pup,
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(val & (~0xf)) | vref_map[0],
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__LINE__));
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}
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}
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interface_state[if_id] = 0;
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}
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/* TODO: Set number of active interfaces */
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num_pup = tm->num_of_bus_per_interface * MAX_INTERFACE_NUM;
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while ((algo_run_flag <= num_pup) & (while_count < 10)) {
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while_count++;
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for (rep = 1; rep < 4; rep++) {
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ddr3_tip_centr_skip_min_win_check = 1;
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ddr3_tip_centralization_rx(dev_num);
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ddr3_tip_centr_skip_min_win_check = 0;
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/* Read Valid window results only for non converge pups */
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for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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if (interface_state[if_id] != 4) {
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get_valid_win_rx(dev_num, if_id, res);
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for (pup = 0;
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pup < tm->num_of_bus_per_interface;
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pup++) {
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VALIDATE_ACTIVE
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(tm->bus_act_mask, pup);
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if (pup_st[pup]
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[if_id] ==
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VREF_CONVERGE)
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continue;
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current_valid_window[pup]
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[if_id] =
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(current_valid_window[pup]
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[if_id] * (rep - 1) +
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1000 * res[pup]) / rep;
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}
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}
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}
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}
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for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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DEBUG_TRAINING_HW_ALG(
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DEBUG_LEVEL_TRACE,
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("current_valid_window: IF[ %d ] - ", if_id));
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for (pup = 0;
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pup < tm->num_of_bus_per_interface; pup++) {
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VALIDATE_ACTIVE(tm->bus_act_mask, pup);
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DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
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("%d ",
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current_valid_window
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[pup][if_id]));
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}
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DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE, ("\n"));
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}
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/* Compare results and respond as function of state */
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for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
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VALIDATE_ACTIVE(tm->if_act_mask, if_id);
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for (pup = 0;
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pup < tm->num_of_bus_per_interface; pup++) {
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VALIDATE_ACTIVE(tm->bus_act_mask, pup);
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DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
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("I/F[ %d ], pup[ %d ] STATE #%d (%d)\n",
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if_id, pup,
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pup_st[pup]
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[if_id], __LINE__));
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if (pup_st[pup][if_id] == VREF_CONVERGE)
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continue;
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DEBUG_TRAINING_HW_ALG(DEBUG_LEVEL_TRACE,
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("I/F[ %d ], pup[ %d ] CHECK progress - Current %d Last %d, limit VREF %d (%d)\n",
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if_id, pup,
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current_valid_window[pup]
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[if_id],
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last_valid_window[pup]
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[if_id], lim_vref[pup]
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[if_id], __LINE__));
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/*
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* The -1 is for solution resolution +/- 1 tap
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* of ADLL
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*/
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if (current_valid_window[pup][if_id] + 200 >=
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(last_valid_window[pup][if_id])) {
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if (pup_st[pup][if_id] == VREF_STEP_1) {
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/*
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* We stay in the same state and
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* step just update the window
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* size (take the max) and Vref
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*/
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if (current_vref[pup]
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[if_id] == VREF_MAX_INDEX) {
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/*
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* If we step to the end
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* and didn't converge
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* to some particular
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* better Vref value
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* define the pup as
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* converge and step
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* back to nominal
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* Vref.
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*/
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pup_st[pup]
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[if_id] =
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VREF_CONVERGE;
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algo_run_flag++;
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interface_state
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[if_id]++;
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DEBUG_TRAINING_HW_ALG
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(DEBUG_LEVEL_TRACE,
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("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
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if_id, pup,
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current_vref[pup]
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[if_id],
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__LINE__));
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} else {
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/* continue to update the Vref index */
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current_vref[pup]
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[if_id] =
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((current_vref[pup]
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[if_id] +
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initial_step) >
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VREF_MAX_INDEX) ?
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VREF_MAX_INDEX
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: (current_vref[pup]
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[if_id] +
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initial_step);
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if (current_vref[pup]
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[if_id] ==
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VREF_MAX_INDEX) {
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pup_st[pup]
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[if_id]
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=
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VREF_STEP_2;
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}
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lim_vref[pup]
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[if_id] =
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last_vref[pup]
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[if_id] =
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current_vref[pup]
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[if_id];
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}
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last_valid_window[pup]
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[if_id] =
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GET_MAX(current_valid_window
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[pup][if_id],
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last_valid_window
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[pup]
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[if_id]);
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/* update the Vref for next stage */
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currrent_vref =
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current_vref[pup]
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[if_id];
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CHECK_STATUS
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(ddr3_tip_bus_read
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(dev_num, if_id,
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ACCESS_TYPE_UNICAST, pup,
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DDR_PHY_DATA, reg_addr,
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&val));
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CHECK_STATUS
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(ddr3_tip_bus_write
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(dev_num,
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ACCESS_TYPE_UNICAST,
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if_id,
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ACCESS_TYPE_UNICAST, pup,
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DDR_PHY_DATA, reg_addr,
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(val & (~0xf)) |
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vref_map[currrent_vref]));
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DEBUG_TRAINING_HW_ALG
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(DEBUG_LEVEL_TRACE,
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("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
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if_id, pup,
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(val & (~0xf)) |
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vref_map[currrent_vref],
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__LINE__));
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} else if (pup_st[pup][if_id]
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== VREF_STEP_2) {
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/*
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* We keep on search back with
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* the same step size.
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*/
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last_valid_window[pup]
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[if_id] =
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GET_MAX(current_valid_window
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[pup][if_id],
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last_valid_window
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[pup]
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[if_id]);
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last_vref[pup][if_id] =
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current_vref[pup]
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[if_id];
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/* we finish all search space */
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if ((current_vref[pup]
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[if_id] - second_step) == lim_vref[pup][if_id]) {
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/*
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* If we step to the end
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* and didn't converge
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* to some particular
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* better Vref value
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* define the pup as
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* converge and step
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* back to nominal
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* Vref.
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*/
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pup_st[pup]
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[if_id] =
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VREF_CONVERGE;
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algo_run_flag++;
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interface_state
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[if_id]++;
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current_vref[pup]
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[if_id] =
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(current_vref[pup]
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[if_id] -
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second_step);
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DEBUG_TRAINING_HW_ALG
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(DEBUG_LEVEL_TRACE,
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("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
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if_id, pup,
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current_vref[pup]
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[if_id],
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__LINE__));
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} else
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/* we finish all search space */
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if (current_vref[pup]
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[if_id] ==
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lim_vref[pup]
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[if_id]) {
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/*
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* If we step to the end
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* and didn't converge
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* to some particular
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* better Vref value
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* define the pup as
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* converge and step
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* back to nominal
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* Vref.
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*/
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pup_st[pup]
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[if_id] =
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VREF_CONVERGE;
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algo_run_flag++;
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interface_state
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[if_id]++;
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DEBUG_TRAINING_HW_ALG
|
|
(DEBUG_LEVEL_TRACE,
|
|
("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
|
|
if_id, pup,
|
|
current_vref[pup]
|
|
[if_id],
|
|
__LINE__));
|
|
} else {
|
|
current_vref[pup]
|
|
[if_id] =
|
|
current_vref[pup]
|
|
[if_id] -
|
|
second_step;
|
|
}
|
|
|
|
/* Update the Vref for next stage */
|
|
currrent_vref =
|
|
current_vref[pup]
|
|
[if_id];
|
|
CHECK_STATUS
|
|
(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr,
|
|
&val));
|
|
CHECK_STATUS
|
|
(ddr3_tip_bus_write
|
|
(dev_num,
|
|
ACCESS_TYPE_UNICAST,
|
|
if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr,
|
|
(val & (~0xf)) |
|
|
vref_map[currrent_vref]));
|
|
DEBUG_TRAINING_HW_ALG
|
|
(DEBUG_LEVEL_TRACE,
|
|
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
|
|
if_id, pup,
|
|
(val & (~0xf)) |
|
|
vref_map[currrent_vref],
|
|
__LINE__));
|
|
}
|
|
} else {
|
|
/* we change state and change step */
|
|
if (pup_st[pup][if_id] == VREF_STEP_1) {
|
|
pup_st[pup][if_id] =
|
|
VREF_STEP_2;
|
|
lim_vref[pup][if_id] =
|
|
current_vref[pup]
|
|
[if_id] - initial_step;
|
|
last_valid_window[pup]
|
|
[if_id] =
|
|
current_valid_window[pup]
|
|
[if_id];
|
|
last_vref[pup][if_id] =
|
|
current_vref[pup]
|
|
[if_id];
|
|
current_vref[pup][if_id] =
|
|
last_vref[pup][if_id] -
|
|
second_step;
|
|
|
|
/* Update the Vref for next stage */
|
|
CHECK_STATUS
|
|
(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr,
|
|
&val));
|
|
CHECK_STATUS
|
|
(ddr3_tip_bus_write
|
|
(dev_num,
|
|
ACCESS_TYPE_UNICAST,
|
|
if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr,
|
|
(val & (~0xf)) |
|
|
vref_map[current_vref[pup]
|
|
[if_id]]));
|
|
DEBUG_TRAINING_HW_ALG
|
|
(DEBUG_LEVEL_TRACE,
|
|
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
|
|
if_id, pup,
|
|
(val & (~0xf)) |
|
|
vref_map[current_vref[pup]
|
|
[if_id]],
|
|
__LINE__));
|
|
|
|
} else if (pup_st[pup][if_id] == VREF_STEP_2) {
|
|
/*
|
|
* The last search was the max
|
|
* point set value and exit
|
|
*/
|
|
CHECK_STATUS
|
|
(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr,
|
|
&val));
|
|
CHECK_STATUS
|
|
(ddr3_tip_bus_write
|
|
(dev_num,
|
|
ACCESS_TYPE_UNICAST,
|
|
if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr,
|
|
(val & (~0xf)) |
|
|
vref_map[last_vref[pup]
|
|
[if_id]]));
|
|
DEBUG_TRAINING_HW_ALG
|
|
(DEBUG_LEVEL_TRACE,
|
|
("VREF config, IF[ %d ]pup[ %d ] - Vref = %X (%d)\n",
|
|
if_id, pup,
|
|
(val & (~0xf)) |
|
|
vref_map[last_vref[pup]
|
|
[if_id]],
|
|
__LINE__));
|
|
pup_st[pup][if_id] =
|
|
VREF_CONVERGE;
|
|
algo_run_flag++;
|
|
interface_state[if_id]++;
|
|
DEBUG_TRAINING_HW_ALG
|
|
(DEBUG_LEVEL_TRACE,
|
|
("I/F[ %d ], pup[ %d ] VREF_CONVERGE - Vref = %X (%d)\n",
|
|
if_id, pup,
|
|
current_vref[pup]
|
|
[if_id], __LINE__));
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
|
|
VALIDATE_ACTIVE(tm->if_act_mask, if_id);
|
|
for (pup = 0;
|
|
pup < tm->num_of_bus_per_interface; pup++) {
|
|
VALIDATE_ACTIVE(tm->bus_act_mask, pup);
|
|
CHECK_STATUS(ddr3_tip_bus_read
|
|
(dev_num, if_id,
|
|
ACCESS_TYPE_UNICAST, pup,
|
|
DDR_PHY_DATA, reg_addr, &val));
|
|
DEBUG_TRAINING_HW_ALG(
|
|
DEBUG_LEVEL_INFO,
|
|
("FINAL values: I/F[ %d ], pup[ %d ] - Vref = %X (%d)\n",
|
|
if_id, pup, val, __LINE__));
|
|
}
|
|
}
|
|
|
|
flow_result[if_id] = TEST_SUCCESS;
|
|
|
|
/* restore start/end pattern */
|
|
start_pattern = copy_start_pattern;
|
|
end_pattern = copy_end_pattern;
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* CK/CA Delay
|
|
*/
|
|
int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap)
|
|
{
|
|
u32 if_id = 0;
|
|
u32 ck_num_adll_tap = 0, ca_num_adll_tap = 0, data = 0;
|
|
struct hws_topology_map *tm = ddr3_get_topology_map();
|
|
|
|
/*
|
|
* ck_delay_table is delaying the of the clock signal only.
|
|
* (to overcome timing issues between_c_k & command/address signals)
|
|
*/
|
|
/*
|
|
* ca_delay is delaying the of the entire command & Address signals
|
|
* (include Clock signal to overcome DGL error on the Clock versus
|
|
* the DQS).
|
|
*/
|
|
|
|
/* Calc ADLL Tap */
|
|
if ((ck_delay == -1) || (ck_delay_16 == -1)) {
|
|
DEBUG_TRAINING_HW_ALG(
|
|
DEBUG_LEVEL_ERROR,
|
|
("ERROR: One of ck_delay values not initialized!!!\n"));
|
|
}
|
|
|
|
for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
|
|
VALIDATE_ACTIVE(tm->if_act_mask, if_id);
|
|
/* Calc delay ps in ADLL tap */
|
|
if (tm->interface_params[if_id].bus_width ==
|
|
BUS_WIDTH_16)
|
|
ck_num_adll_tap = ck_delay_16 / adll_tap;
|
|
else
|
|
ck_num_adll_tap = ck_delay / adll_tap;
|
|
|
|
ca_num_adll_tap = ca_delay / adll_tap;
|
|
data = (ck_num_adll_tap & 0x3f) +
|
|
((ca_num_adll_tap & 0x3f) << 10);
|
|
|
|
/*
|
|
* Set the ADLL number to the CK ADLL for Interfaces for
|
|
* all Pup
|
|
*/
|
|
DEBUG_TRAINING_HW_ALG(
|
|
DEBUG_LEVEL_TRACE,
|
|
("ck_num_adll_tap %d ca_num_adll_tap %d adll_tap %d\n",
|
|
ck_num_adll_tap, ca_num_adll_tap, adll_tap));
|
|
|
|
CHECK_STATUS(ddr3_tip_bus_write(dev_num, ACCESS_TYPE_UNICAST,
|
|
if_id, ACCESS_TYPE_MULTICAST,
|
|
PARAM_NOT_CARE, DDR_PHY_CONTROL,
|
|
0x0, data));
|
|
}
|
|
|
|
return MV_OK;
|
|
}
|