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u-boot-brain/board/freescale/mpc8572ds
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Haiying Wang b5f65dfa9a Some changes of TLB entry setting for MPC8572DS 
- Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode,
all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0
can not access PIXIS_BASE anymore (any access will cause DataTLBError exception)

- Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board.

Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
2009-01-13 16:58:46 -06:00
..
config.mk mpc85xx: Add support for the MPC8572DS reference board 2008-08-27 11:43:53 -05:00
ddr.c Add ddr interleaving suppport for MPC8572DS board 2008-10-18 21:54:05 +02:00
law.c NAND: Add support for MPC8572DS board 2008-10-29 13:08:17 -05:00
Makefile mpc85xx: Add support for the MPC8572DS reference board 2008-08-27 11:43:53 -05:00
mpc8572ds.c PCIE2 and PCIE3 are decided by corresponing bit in devdisr instead of PCIE1 bit 2009-01-13 16:32:52 -06:00
tlb.c Some changes of TLB entry setting for MPC8572DS 2009-01-13 16:58:46 -06:00
u-boot.lds mpc85xx: Add support for the MPC8572DS reference board 2008-08-27 11:43:53 -05:00