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https://github.com/brain-hackers/u-boot-brain
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8b295a2026
The default timeout value had been left in order to leave some traces about default setup of watchdog done by firmware. For better understanding and compiler burden, replace it with a comment. Suggested-by: Stefan Roese <sr@denx.de> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
76 lines
1.6 KiB
C
76 lines
1.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 Intel Corporation
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/scu.h>
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/* Hardware timeout in seconds */
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#define WDT_PRETIMEOUT 15
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#define WDT_TIMEOUT_MIN (1 + WDT_PRETIMEOUT)
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#define WDT_TIMEOUT_MAX 170
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/*
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* Note, firmware chooses 90 seconds as a default timeout for watchdog on
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* Intel Tangier SoC. It means that without handling it in the running code
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* the reboot will happen.
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*/
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#ifndef CONFIG_WATCHDOG_TIMEOUT_MSECS
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#define WATCHDOG_HEARTBEAT 60000
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#else
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#define WATCHDOG_HEARTBEAT CONFIG_WATCHDOG_TIMEOUT_MSECS
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#endif
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enum {
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SCU_WATCHDOG_START = 0,
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SCU_WATCHDOG_STOP = 1,
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SCU_WATCHDOG_KEEPALIVE = 2,
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SCU_WATCHDOG_SET_ACTION_ON_TIMEOUT = 3,
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};
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void hw_watchdog_reset(void)
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{
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static unsigned long last;
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unsigned long now;
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if (gd->timer)
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now = timer_get_us();
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else
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now = rdtsc() / 1000;
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/* Do not flood SCU */
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if (last > now)
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last = 0;
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if (unlikely((now - last) > (WDT_PRETIMEOUT / 2) * 1000000)) {
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last = now;
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scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_KEEPALIVE);
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}
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}
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int hw_watchdog_disable(void)
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{
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return scu_ipc_simple_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_STOP);
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}
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void hw_watchdog_init(void)
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{
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u32 timeout = WATCHDOG_HEARTBEAT / 1000;
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int in_size;
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struct ipc_wd_start {
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u32 pretimeout;
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u32 timeout;
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} ipc_wd_start = { timeout - WDT_PRETIMEOUT, timeout };
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/*
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* SCU expects the input size for watchdog IPC
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* to be based on 4 bytes
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*/
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in_size = DIV_ROUND_UP(sizeof(ipc_wd_start), 4);
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scu_ipc_command(IPCMSG_WATCHDOG_TIMER, SCU_WATCHDOG_START,
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(u32 *)&ipc_wd_start, in_size, NULL, 0);
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}
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