96 lines
1.9 KiB
C
96 lines
1.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* U-Boot syscon driver for SiFive's Core Local Interruptor (CLINT).
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* The CLINT block holds memory-mapped control and status registers
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* associated with software and timer interrupts.
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <timer.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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#include <linux/err.h>
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/* MSIP registers */
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#define MSIP_REG(base, hart) ((ulong)(base) + (hart) * 4)
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/* mtime compare register */
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#define MTIMECMP_REG(base, hart) ((ulong)(base) + 0x4000 + (hart) * 8)
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/* mtime register */
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#define MTIME_REG(base) ((ulong)(base) + 0xbff8)
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DECLARE_GLOBAL_DATA_PTR;
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int riscv_init_ipi(void)
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{
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int ret;
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struct udevice *dev;
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ret = uclass_get_device_by_driver(UCLASS_TIMER,
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DM_GET_DRIVER(sifive_clint), &dev);
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if (ret)
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return ret;
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gd->arch.clint = dev_read_addr_ptr(dev);
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if (!gd->arch.clint)
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return -EINVAL;
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return 0;
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}
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int riscv_send_ipi(int hart)
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{
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writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_clear_ipi(int hart)
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{
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writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
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return 0;
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}
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static u64 sifive_clint_get_count(struct udevice *dev)
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{
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return readq((void __iomem *)MTIME_REG(dev->priv));
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}
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static const struct timer_ops sifive_clint_ops = {
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.get_count = sifive_clint_get_count,
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};
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static int sifive_clint_probe(struct udevice *dev)
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{
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dev->priv = dev_read_addr_ptr(dev);
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if (!dev->priv)
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return -EINVAL;
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return timer_timebase_fallback(dev);
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}
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static const struct udevice_id sifive_clint_ids[] = {
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{ .compatible = "riscv,clint0" },
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{ }
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};
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U_BOOT_DRIVER(sifive_clint) = {
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.name = "sifive_clint",
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.id = UCLASS_TIMER,
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.of_match = sifive_clint_ids,
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.probe = sifive_clint_probe,
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.ops = &sifive_clint_ops,
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.flags = DM_FLAG_PRE_RELOC,
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};
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