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https://github.com/brain-hackers/u-boot-brain
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18c0144542
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework.
here, PBL initialise the internal SRAM and copy SPL(160KB). This further
initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR.
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
27 lines
496 B
INI
27 lines
496 B
INI
#PBI commands
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#Initialize CPC1
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09010000 00200400
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09138000 00000000
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091380c0 00000100
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#Configure CPC1 as 256KB SRAM
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09010100 00000000
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09010104 fffc0007
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09010f00 08000000
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09010000 80000000
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#Configure LAW for CPC1
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09000cd0 00000000
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09000cd4 fffc0000
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09000cd8 81000011
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#Configure alternate space
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09000010 00000000
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09000014 ff000000
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09000018 81000000
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#Configure SPI controller
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09110000 80000403
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09110020 2d170008
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09110024 00100008
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09110028 00100008
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0911002c 00100008
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#Flush PBL data
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091380c0 000FFFFF
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