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![Jagan Teki](/assets/img/avatar_default.png)
Make rx mode flags as generic to spi, earlier mode_rx is maintained separately because of some flash specific code. Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Cc: Vignesh R <vigneshr@ti.com> Cc: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Jagan Teki <jteki@openedev.com>
704 lines
18 KiB
C
704 lines
18 KiB
C
/*
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* Copyright (c) 2011-12 The Chromium OS Authors.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* This file is derived from the flashrom project.
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <pch.h>
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#include <pci.h>
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#include <pci_ids.h>
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#include <spi.h>
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#include <asm/io.h>
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#include "ich.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef DEBUG_TRACE
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#define debug_trace(fmt, args...) debug(fmt, ##args)
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#else
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#define debug_trace(x, args...)
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#endif
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static u8 ich_readb(struct ich_spi_priv *priv, int reg)
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{
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u8 value = readb(priv->base + reg);
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debug_trace("read %2.2x from %4.4x\n", value, reg);
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return value;
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}
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static u16 ich_readw(struct ich_spi_priv *priv, int reg)
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{
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u16 value = readw(priv->base + reg);
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debug_trace("read %4.4x from %4.4x\n", value, reg);
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return value;
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}
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static u32 ich_readl(struct ich_spi_priv *priv, int reg)
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{
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u32 value = readl(priv->base + reg);
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debug_trace("read %8.8x from %4.4x\n", value, reg);
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return value;
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}
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static void ich_writeb(struct ich_spi_priv *priv, u8 value, int reg)
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{
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writeb(value, priv->base + reg);
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debug_trace("wrote %2.2x to %4.4x\n", value, reg);
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}
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static void ich_writew(struct ich_spi_priv *priv, u16 value, int reg)
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{
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writew(value, priv->base + reg);
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debug_trace("wrote %4.4x to %4.4x\n", value, reg);
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}
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static void ich_writel(struct ich_spi_priv *priv, u32 value, int reg)
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{
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writel(value, priv->base + reg);
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debug_trace("wrote %8.8x to %4.4x\n", value, reg);
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}
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static void write_reg(struct ich_spi_priv *priv, const void *value,
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int dest_reg, uint32_t size)
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{
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memcpy_toio(priv->base + dest_reg, value, size);
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}
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static void read_reg(struct ich_spi_priv *priv, int src_reg, void *value,
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uint32_t size)
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{
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memcpy_fromio(value, priv->base + src_reg, size);
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}
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static void ich_set_bbar(struct ich_spi_priv *ctlr, uint32_t minaddr)
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{
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const uint32_t bbar_mask = 0x00ffff00;
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uint32_t ichspi_bbar;
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minaddr &= bbar_mask;
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ichspi_bbar = ich_readl(ctlr, ctlr->bbar) & ~bbar_mask;
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ichspi_bbar |= minaddr;
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ich_writel(ctlr, ichspi_bbar, ctlr->bbar);
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}
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/* @return 1 if the SPI flash supports the 33MHz speed */
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static int ich9_can_do_33mhz(struct udevice *dev)
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{
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u32 fdod, speed;
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/* Observe SPI Descriptor Component Section 0 */
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dm_pci_write_config32(dev->parent, 0xb0, 0x1000);
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/* Extract the Write/Erase SPI Frequency from descriptor */
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dm_pci_read_config32(dev->parent, 0xb4, &fdod);
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/* Bits 23:21 have the fast read clock frequency, 0=20MHz, 1=33MHz */
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speed = (fdod >> 21) & 7;
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return speed == 1;
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}
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static int ich_init_controller(struct udevice *dev,
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struct ich_spi_platdata *plat,
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struct ich_spi_priv *ctlr)
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{
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ulong sbase_addr;
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void *sbase;
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/* SBASE is similar */
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pch_get_spi_base(dev->parent, &sbase_addr);
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sbase = (void *)sbase_addr;
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debug("%s: sbase=%p\n", __func__, sbase);
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if (plat->ich_version == ICHV_7) {
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struct ich7_spi_regs *ich7_spi = sbase;
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ich7_spi = (struct ich7_spi_regs *)sbase;
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ctlr->ichspi_lock = readw(&ich7_spi->spis) & SPIS_LOCK;
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ctlr->opmenu = offsetof(struct ich7_spi_regs, opmenu);
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ctlr->menubytes = sizeof(ich7_spi->opmenu);
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ctlr->optype = offsetof(struct ich7_spi_regs, optype);
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ctlr->addr = offsetof(struct ich7_spi_regs, spia);
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ctlr->data = offsetof(struct ich7_spi_regs, spid);
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ctlr->databytes = sizeof(ich7_spi->spid);
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ctlr->status = offsetof(struct ich7_spi_regs, spis);
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ctlr->control = offsetof(struct ich7_spi_regs, spic);
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ctlr->bbar = offsetof(struct ich7_spi_regs, bbar);
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ctlr->preop = offsetof(struct ich7_spi_regs, preop);
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ctlr->base = ich7_spi;
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} else if (plat->ich_version == ICHV_9) {
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struct ich9_spi_regs *ich9_spi = sbase;
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ctlr->ichspi_lock = readw(&ich9_spi->hsfs) & HSFS_FLOCKDN;
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ctlr->opmenu = offsetof(struct ich9_spi_regs, opmenu);
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ctlr->menubytes = sizeof(ich9_spi->opmenu);
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ctlr->optype = offsetof(struct ich9_spi_regs, optype);
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ctlr->addr = offsetof(struct ich9_spi_regs, faddr);
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ctlr->data = offsetof(struct ich9_spi_regs, fdata);
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ctlr->databytes = sizeof(ich9_spi->fdata);
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ctlr->status = offsetof(struct ich9_spi_regs, ssfs);
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ctlr->control = offsetof(struct ich9_spi_regs, ssfc);
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ctlr->speed = ctlr->control + 2;
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ctlr->bbar = offsetof(struct ich9_spi_regs, bbar);
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ctlr->preop = offsetof(struct ich9_spi_regs, preop);
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ctlr->bcr = offsetof(struct ich9_spi_regs, bcr);
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ctlr->pr = &ich9_spi->pr[0];
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ctlr->base = ich9_spi;
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} else {
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debug("ICH SPI: Unrecognised ICH version %d\n",
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plat->ich_version);
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return -EINVAL;
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}
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/* Work out the maximum speed we can support */
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ctlr->max_speed = 20000000;
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if (plat->ich_version == ICHV_9 && ich9_can_do_33mhz(dev))
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ctlr->max_speed = 33000000;
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debug("ICH SPI: Version ID %d detected at %p, speed %ld\n",
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plat->ich_version, ctlr->base, ctlr->max_speed);
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ich_set_bbar(ctlr, 0);
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return 0;
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}
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static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
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{
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trans->out += bytes;
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trans->bytesout -= bytes;
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}
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static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
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{
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trans->in += bytes;
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trans->bytesin -= bytes;
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}
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static void spi_setup_type(struct spi_trans *trans, int data_bytes)
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{
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trans->type = 0xFF;
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/* Try to guess spi type from read/write sizes */
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if (trans->bytesin == 0) {
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if (trans->bytesout + data_bytes > 4)
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/*
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* If bytesin = 0 and bytesout > 4, we presume this is
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* a write data operation, which is accompanied by an
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* address.
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*/
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 1) { /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 4) /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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/* Fast read command is called with 5 bytes instead of 4 */
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if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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--trans->bytesout;
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}
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}
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static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans)
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{
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uint16_t optypes;
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uint8_t opmenu[ctlr->menubytes];
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trans->opcode = trans->out[0];
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spi_use_out(trans, 1);
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if (!ctlr->ichspi_lock) {
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/* The lock is off, so just use index 0. */
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ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
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optypes = ich_readw(ctlr, ctlr->optype);
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optypes = (optypes & 0xfffc) | (trans->type & 0x3);
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ich_writew(ctlr, optypes, ctlr->optype);
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return 0;
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} else {
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/* The lock is on. See if what we need is on the menu. */
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uint8_t optype;
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uint16_t opcode_index;
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/* Write Enable is handled as atomic prefix */
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if (trans->opcode == SPI_OPCODE_WREN)
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return 0;
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read_reg(ctlr, ctlr->opmenu, opmenu, sizeof(opmenu));
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for (opcode_index = 0; opcode_index < ctlr->menubytes;
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opcode_index++) {
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if (opmenu[opcode_index] == trans->opcode)
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break;
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}
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if (opcode_index == ctlr->menubytes) {
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printf("ICH SPI: Opcode %x not found\n",
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trans->opcode);
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return -EINVAL;
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}
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optypes = ich_readw(ctlr, ctlr->optype);
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optype = (optypes >> (opcode_index * 2)) & 0x3;
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if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
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optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
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trans->bytesout >= 3) {
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/* We guessed wrong earlier. Fix it up. */
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trans->type = optype;
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}
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if (optype != trans->type) {
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printf("ICH SPI: Transaction doesn't fit type %d\n",
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optype);
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return -ENOSPC;
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}
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return opcode_index;
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}
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}
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static int spi_setup_offset(struct spi_trans *trans)
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{
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/* Separate the SPI address and data */
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switch (trans->type) {
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case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
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return 0;
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case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
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trans->offset = ((uint32_t)trans->out[0] << 16) |
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((uint32_t)trans->out[1] << 8) |
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((uint32_t)trans->out[2] << 0);
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spi_use_out(trans, 3);
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return 1;
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default:
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printf("Unrecognized SPI transaction type %#x\n", trans->type);
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return -EPROTO;
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}
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}
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/*
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* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
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* below is true) or 0. In case the wait was for the bit(s) to set - write
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* those bits back, which would cause resetting them.
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*
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* Return the last read status value on success or -1 on failure.
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*/
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static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
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int wait_til_set)
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{
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int timeout = 600000; /* This will result in 6s */
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u16 status = 0;
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while (timeout--) {
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status = ich_readw(ctlr, ctlr->status);
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if (wait_til_set ^ ((status & bitmask) == 0)) {
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if (wait_til_set) {
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ich_writew(ctlr, status & bitmask,
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ctlr->status);
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}
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return status;
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}
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udelay(10);
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}
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printf("ICH SPI: SCIP timeout, read %x, expected %x\n",
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status, bitmask);
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return -ETIMEDOUT;
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}
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static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct ich_spi_platdata *plat = dev_get_platdata(bus);
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struct ich_spi_priv *ctlr = dev_get_priv(bus);
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uint16_t control;
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int16_t opcode_index;
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int with_address;
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int status;
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int bytes = bitlen / 8;
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struct spi_trans *trans = &ctlr->trans;
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unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
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int using_cmd = 0;
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int ret;
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/* We don't support writing partial bytes */
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if (bitlen % 8) {
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debug("ICH SPI: Accessing partial bytes not supported\n");
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return -EPROTONOSUPPORT;
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}
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/* An empty end transaction can be ignored */
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if (type == SPI_XFER_END && !dout && !din)
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return 0;
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if (type & SPI_XFER_BEGIN)
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memset(trans, '\0', sizeof(*trans));
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/* Dp we need to come back later to finish it? */
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if (dout && type == SPI_XFER_BEGIN) {
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if (bytes > ICH_MAX_CMD_LEN) {
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debug("ICH SPI: Command length limit exceeded\n");
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return -ENOSPC;
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}
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memcpy(trans->cmd, dout, bytes);
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trans->cmd_len = bytes;
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debug_trace("ICH SPI: Saved %d bytes\n", bytes);
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return 0;
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}
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/*
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* We process a 'middle' spi_xfer() call, which has no
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* SPI_XFER_BEGIN/END, as an independent transaction as if it had
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* an end. We therefore repeat the command. This is because ICH
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* seems to have no support for this, or because interest (in digging
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* out the details and creating a special case in the code) is low.
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*/
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if (trans->cmd_len) {
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trans->out = trans->cmd;
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trans->bytesout = trans->cmd_len;
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using_cmd = 1;
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debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
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} else {
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trans->out = dout;
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trans->bytesout = dout ? bytes : 0;
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}
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trans->in = din;
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trans->bytesin = din ? bytes : 0;
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/* There has to always at least be an opcode */
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if (!trans->bytesout) {
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debug("ICH SPI: No opcode for transfer\n");
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return -EPROTO;
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}
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ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
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if (ret < 0)
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return ret;
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if (plat->ich_version == ICHV_7)
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ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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else
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ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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spi_setup_type(trans, using_cmd ? bytes : 0);
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opcode_index = spi_setup_opcode(ctlr, trans);
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if (opcode_index < 0)
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return -EINVAL;
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with_address = spi_setup_offset(trans);
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if (with_address < 0)
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return -EINVAL;
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if (trans->opcode == SPI_OPCODE_WREN) {
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/*
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* Treat Write Enable as Atomic Pre-Op if possible
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* in order to prevent the Management Engine from
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* issuing a transaction between WREN and DATA.
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*/
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if (!ctlr->ichspi_lock)
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ich_writew(ctlr, trans->opcode, ctlr->preop);
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return 0;
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}
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if (ctlr->speed && ctlr->max_speed >= 33000000) {
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int byte;
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byte = ich_readb(ctlr, ctlr->speed);
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if (ctlr->cur_speed >= 33000000)
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byte |= SSFC_SCF_33MHZ;
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else
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byte &= ~SSFC_SCF_33MHZ;
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ich_writeb(ctlr, byte, ctlr->speed);
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}
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/* See if we have used up the command data */
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if (using_cmd && dout && bytes) {
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trans->out = dout;
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trans->bytesout = bytes;
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debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
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}
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/* Preset control fields */
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control = ich_readw(ctlr, ctlr->control);
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control &= ~SSFC_RESERVED;
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control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
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/* Issue atomic preop cycle if needed */
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if (ich_readw(ctlr, ctlr->preop))
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control |= SPIC_ACS;
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if (!trans->bytesout && !trans->bytesin) {
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/* SPI addresses are 24 bit only */
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if (with_address) {
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ich_writel(ctlr, trans->offset & 0x00FFFFFF,
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ctlr->addr);
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}
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/*
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* This is a 'no data' command (like Write Enable), its
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* bitesout size was 1, decremented to zero while executing
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* spi_setup_opcode() above. Tell the chip to send the
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* command.
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*/
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ich_writew(ctlr, control, ctlr->control);
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/* wait for the result */
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status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
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if (status < 0)
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return status;
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if (status & SPIS_FCERR) {
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debug("ICH SPI: Command transaction error\n");
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return -EIO;
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}
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return 0;
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}
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/*
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* Check if this is a write command atempting to transfer more bytes
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* than the controller can handle. Iterations for writes are not
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* supported here because each SPI write command needs to be preceded
|
|
* and followed by other SPI commands, and this sequence is controlled
|
|
* by the SPI chip driver.
|
|
*/
|
|
if (trans->bytesout > ctlr->databytes) {
|
|
debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
|
|
return -EPROTO;
|
|
}
|
|
|
|
/*
|
|
* Read or write up to databytes bytes at a time until everything has
|
|
* been sent.
|
|
*/
|
|
while (trans->bytesout || trans->bytesin) {
|
|
uint32_t data_length;
|
|
|
|
/* SPI addresses are 24 bit only */
|
|
ich_writel(ctlr, trans->offset & 0x00FFFFFF, ctlr->addr);
|
|
|
|
if (trans->bytesout)
|
|
data_length = min(trans->bytesout, ctlr->databytes);
|
|
else
|
|
data_length = min(trans->bytesin, ctlr->databytes);
|
|
|
|
/* Program data into FDATA0 to N */
|
|
if (trans->bytesout) {
|
|
write_reg(ctlr, trans->out, ctlr->data, data_length);
|
|
spi_use_out(trans, data_length);
|
|
if (with_address)
|
|
trans->offset += data_length;
|
|
}
|
|
|
|
/* Add proper control fields' values */
|
|
control &= ~((ctlr->databytes - 1) << 8);
|
|
control |= SPIC_DS;
|
|
control |= (data_length - 1) << 8;
|
|
|
|
/* write it */
|
|
ich_writew(ctlr, control, ctlr->control);
|
|
|
|
/* Wait for Cycle Done Status or Flash Cycle Error */
|
|
status = ich_status_poll(ctlr, SPIS_CDS | SPIS_FCERR, 1);
|
|
if (status < 0)
|
|
return status;
|
|
|
|
if (status & SPIS_FCERR) {
|
|
debug("ICH SPI: Data transaction error %x\n", status);
|
|
return -EIO;
|
|
}
|
|
|
|
if (trans->bytesin) {
|
|
read_reg(ctlr, ctlr->data, trans->in, data_length);
|
|
spi_use_in(trans, data_length);
|
|
if (with_address)
|
|
trans->offset += data_length;
|
|
}
|
|
}
|
|
|
|
/* Clear atomic preop now that xfer is done */
|
|
ich_writew(ctlr, 0, ctlr->preop);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This uses the SPI controller from the Intel Cougar Point and Panther Point
|
|
* PCH to write-protect portions of the SPI flash until reboot. The changes
|
|
* don't actually take effect until the HSFS[FLOCKDN] bit is set, but that's
|
|
* done elsewhere.
|
|
*/
|
|
int spi_write_protect_region(struct udevice *dev, uint32_t lower_limit,
|
|
uint32_t length, int hint)
|
|
{
|
|
struct udevice *bus = dev->parent;
|
|
struct ich_spi_priv *ctlr = dev_get_priv(bus);
|
|
uint32_t tmplong;
|
|
uint32_t upper_limit;
|
|
|
|
if (!ctlr->pr) {
|
|
printf("%s: operation not supported on this chipset\n",
|
|
__func__);
|
|
return -ENOSYS;
|
|
}
|
|
|
|
if (length == 0 ||
|
|
lower_limit > (0xFFFFFFFFUL - length) + 1 ||
|
|
hint < 0 || hint > 4) {
|
|
printf("%s(0x%x, 0x%x, %d): invalid args\n", __func__,
|
|
lower_limit, length, hint);
|
|
return -EPERM;
|
|
}
|
|
|
|
upper_limit = lower_limit + length - 1;
|
|
|
|
/*
|
|
* Determine bits to write, as follows:
|
|
* 31 Write-protection enable (includes erase operation)
|
|
* 30:29 reserved
|
|
* 28:16 Upper Limit (FLA address bits 24:12, with 11:0 == 0xfff)
|
|
* 15 Read-protection enable
|
|
* 14:13 reserved
|
|
* 12:0 Lower Limit (FLA address bits 24:12, with 11:0 == 0x000)
|
|
*/
|
|
tmplong = 0x80000000 |
|
|
((upper_limit & 0x01fff000) << 4) |
|
|
((lower_limit & 0x01fff000) >> 12);
|
|
|
|
printf("%s: writing 0x%08x to %p\n", __func__, tmplong,
|
|
&ctlr->pr[hint]);
|
|
ctlr->pr[hint] = tmplong;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_probe(struct udevice *dev)
|
|
{
|
|
struct ich_spi_platdata *plat = dev_get_platdata(dev);
|
|
struct ich_spi_priv *priv = dev_get_priv(dev);
|
|
uint8_t bios_cntl;
|
|
int ret;
|
|
|
|
ret = ich_init_controller(dev, plat, priv);
|
|
if (ret)
|
|
return ret;
|
|
/* Disable the BIOS write protect so write commands are allowed */
|
|
ret = pch_set_spi_protect(dev->parent, false);
|
|
if (ret == -ENOSYS) {
|
|
bios_cntl = ich_readb(priv, priv->bcr);
|
|
bios_cntl &= ~BIT(5); /* clear Enable InSMM_STS (EISS) */
|
|
bios_cntl |= 1; /* Write Protect Disable (WPD) */
|
|
ich_writeb(priv, bios_cntl, priv->bcr);
|
|
} else if (ret) {
|
|
debug("%s: Failed to disable write-protect: err=%d\n",
|
|
__func__, ret);
|
|
return ret;
|
|
}
|
|
|
|
priv->cur_speed = priv->max_speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
|
|
priv->cur_speed = speed;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
debug("%s: mode=%d\n", __func__, mode);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_child_pre_probe(struct udevice *dev)
|
|
{
|
|
struct udevice *bus = dev_get_parent(dev);
|
|
struct ich_spi_platdata *plat = dev_get_platdata(bus);
|
|
struct ich_spi_priv *priv = dev_get_priv(bus);
|
|
struct spi_slave *slave = dev_get_parent_priv(dev);
|
|
|
|
/*
|
|
* Yes this controller can only write a small number of bytes at
|
|
* once! The limit is typically 64 bytes.
|
|
*/
|
|
slave->max_write_size = priv->databytes;
|
|
/*
|
|
* ICH 7 SPI controller only supports array read command
|
|
* and byte program command for SST flash
|
|
*/
|
|
if (plat->ich_version == ICHV_7)
|
|
slave->mode = SPI_RX_SLOW | SPI_TX_BYTE;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ich_spi_ofdata_to_platdata(struct udevice *dev)
|
|
{
|
|
struct ich_spi_platdata *plat = dev_get_platdata(dev);
|
|
int ret;
|
|
|
|
ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
|
|
"intel,ich7-spi");
|
|
if (ret == 0) {
|
|
plat->ich_version = ICHV_7;
|
|
} else {
|
|
ret = fdt_node_check_compatible(gd->fdt_blob, dev->of_offset,
|
|
"intel,ich9-spi");
|
|
if (ret == 0)
|
|
plat->ich_version = ICHV_9;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static const struct dm_spi_ops ich_spi_ops = {
|
|
.xfer = ich_spi_xfer,
|
|
.set_speed = ich_spi_set_speed,
|
|
.set_mode = ich_spi_set_mode,
|
|
/*
|
|
* cs_info is not needed, since we require all chip selects to be
|
|
* in the device tree explicitly
|
|
*/
|
|
};
|
|
|
|
static const struct udevice_id ich_spi_ids[] = {
|
|
{ .compatible = "intel,ich7-spi" },
|
|
{ .compatible = "intel,ich9-spi" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(ich_spi) = {
|
|
.name = "ich_spi",
|
|
.id = UCLASS_SPI,
|
|
.of_match = ich_spi_ids,
|
|
.ops = &ich_spi_ops,
|
|
.ofdata_to_platdata = ich_spi_ofdata_to_platdata,
|
|
.platdata_auto_alloc_size = sizeof(struct ich_spi_platdata),
|
|
.priv_auto_alloc_size = sizeof(struct ich_spi_priv),
|
|
.child_pre_probe = ich_spi_child_pre_probe,
|
|
.probe = ich_spi_probe,
|
|
};
|