mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-28 04:48:52 +09:00
461 lines
11 KiB
C
461 lines
11 KiB
C
/*
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* Copyright 2004 Freescale Semiconductor.
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* (C) Copyright 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <i2c.h>
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#include <spd.h>
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#include <asm/mmu.h>
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#if defined(CONFIG_DDR_ECC)
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extern void dma_init (void);
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extern uint dma_check(void);
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extern int dma_xfer (void *dest, uint count, void *src);
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#endif
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#ifdef CONFIG_SPD_EEPROM
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#ifndef CFG_READ_SPD
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#define CFG_READ_SPD i2c_read
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#endif
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/*
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* Convert picoseconds into clock cycles (rounding up if needed).
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*/
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int
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picos_to_clk(int picos)
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{
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int clks;
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clks = picos / (2000000000 / (get_bus_freq(0) / 1000));
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if (picos % (2000000000 / (get_bus_freq(0) / 1000)) != 0) {
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clks++;
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}
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return clks;
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}
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unsigned int
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banksize(unsigned char row_dens)
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{
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return ((row_dens >> 2) | ((row_dens & 3) << 6)) << 24;
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}
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long int
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spd_sdram(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_ddr_t *ddr = &immap->im_ddr;
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volatile ccsr_local_ecm_t *ecm = &immap->im_local_ecm;
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spd_eeprom_t spd;
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unsigned tmp, tmp1;
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unsigned int memsize;
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unsigned int tlb_size;
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unsigned int law_size;
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unsigned char caslat;
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unsigned int ram_tlb_index;
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unsigned int ram_tlb_address;
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CFG_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
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if (spd.nrows > 2) {
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puts("DDR:Only two chip selects are supported on ADS.\n");
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return 0;
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}
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if (spd.nrow_addr < 12
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|| spd.nrow_addr > 14
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|| spd.ncol_addr < 8
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|| spd.ncol_addr > 11) {
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puts("DDR:Row or Col number unsupported.\n");
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return 0;
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}
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ddr->cs0_bnds = (banksize(spd.row_dens) >> 24) - 1;
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ddr->cs0_config = ( 1 << 31
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| (spd.nrow_addr - 12) << 8
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| (spd.ncol_addr - 8) );
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debug("\n");
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debug("cs0_bnds = 0x%08x\n",ddr->cs0_bnds);
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debug("cs0_config = 0x%08x\n",ddr->cs0_config);
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if (spd.nrows == 2) {
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ddr->cs1_bnds = ( (banksize(spd.row_dens) >> 8)
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| ((banksize(spd.row_dens) >> 23) - 1) );
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ddr->cs1_config = ( 1<<31
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| (spd.nrow_addr-12) << 8
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| (spd.ncol_addr-8) );
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debug("cs1_bnds = 0x%08x\n",ddr->cs1_bnds);
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debug("cs1_config = 0x%08x\n",ddr->cs1_config);
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}
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if (spd.mem_type != 0x07) {
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puts("No DDR module found!\n");
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return 0;
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}
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/*
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* Figure out memory size in Megabytes.
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*/
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memsize = spd.nrows * banksize(spd.row_dens) / 0x100000;
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/*
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* First supported LAW size is 16M, at LAWAR_SIZE_16M == 23. Fnord.
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*/
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law_size = 19 + __ilog2(memsize);
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/*
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* Determine size of each TLB1 entry.
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*/
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switch (memsize) {
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case 16:
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case 32:
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tlb_size = BOOKE_PAGESZ_16M;
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break;
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case 64:
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case 128:
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tlb_size = BOOKE_PAGESZ_64M;
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break;
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case 256:
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case 512:
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case 1024:
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case 2048:
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tlb_size = BOOKE_PAGESZ_256M;
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break;
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default:
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puts("DDR: only 16M,32M,64M,128M,256M,512M,1G and 2G DDR I are supported.\n");
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return 0;
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break;
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}
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/*
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* Configure DDR TLB1 entries.
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* Starting at TLB1 8, use no more than 8 TLB1 entries.
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*/
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ram_tlb_index = 8;
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ram_tlb_address = (unsigned int)CFG_DDR_SDRAM_BASE;
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while (ram_tlb_address < (memsize * 1024 * 1024)
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&& ram_tlb_index < 16) {
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mtspr(MAS0, TLB1_MAS0(1, ram_tlb_index, 0));
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mtspr(MAS1, TLB1_MAS1(1, 1, 0, 0, tlb_size));
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mtspr(MAS2, TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
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0, 0, 0, 0, 0, 0, 0, 0));
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mtspr(MAS3, TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
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0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
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asm volatile("isync;msync;tlbwe;isync");
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debug("DDR:MAS0=0x%08x\n", TLB1_MAS0(1, ram_tlb_index, 0));
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debug("DDR:MAS1=0x%08x\n", TLB1_MAS1(1, 1, 0, 0, tlb_size));
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debug("DDR:MAS2=0x%08x\n",
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TLB1_MAS2(E500_TLB_EPN(ram_tlb_address),
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0, 0, 0, 0, 0, 0, 0, 0));
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debug("DDR:MAS3=0x%08x\n",
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TLB1_MAS3(E500_TLB_RPN(ram_tlb_address),
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0, 0, 0, 0, 0, 1, 0, 1, 0, 1));
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ram_tlb_address += (0x1000 << ((tlb_size - 1) * 2));
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ram_tlb_index++;
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}
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/*
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* Set up LAWBAR for all of DDR.
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*/
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ecm->lawbar1 = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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ecm->lawar1 = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size));
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debug("DDR:LAWBAR1=0x%08x\n", ecm->lawbar1);
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debug("DDR:LARAR1=0x%08x\n", ecm->lawar1);
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/*
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* find the largest CAS
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*/
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if(spd.cas_lat & 0x40) {
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caslat = 7;
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} else if (spd.cas_lat & 0x20) {
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caslat = 6;
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} else if (spd.cas_lat & 0x10) {
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caslat = 5;
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} else if (spd.cas_lat & 0x08) {
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caslat = 4;
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} else if (spd.cas_lat & 0x04) {
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caslat = 3;
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} else if (spd.cas_lat & 0x02) {
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caslat = 2;
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} else if (spd.cas_lat & 0x01) {
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caslat = 1;
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} else {
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puts("DDR:no valid CAS Latency information.\n");
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return 0;
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}
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tmp = 20000 / (((spd.clk_cycle & 0xF0) >> 4) * 10
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+ (spd.clk_cycle & 0x0f));
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debug("DDR:Module maximum data rate is: %dMhz\n", tmp);
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tmp1 = get_bus_freq(0) / 1000000;
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if (tmp1 < 230 && tmp1 >= 90 && tmp >= 230) {
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/* 90~230 range, treated as DDR 200 */
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if (spd.clk_cycle3 == 0xa0)
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caslat -= 2;
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else if(spd.clk_cycle2 == 0xa0)
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caslat--;
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} else if (tmp1 < 280 && tmp1 >= 230 && tmp >= 280) {
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/* 230-280 range, treated as DDR 266 */
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if (spd.clk_cycle3 == 0x75)
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x75)
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caslat--;
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} else if (tmp1 < 350 && tmp1 >= 280 && tmp >= 350) {
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/* 280~350 range, treated as DDR 333 */
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if (spd.clk_cycle3 == 0x60)
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caslat -= 2;
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else if (spd.clk_cycle2 == 0x60)
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caslat--;
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} else if (tmp1 < 90 || tmp1 >= 350) {
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/* DDR rate out-of-range */
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puts("DDR:platform frequency is not fit for DDR rate\n");
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return 0;
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}
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/*
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* note: caslat must also be programmed into ddr->sdram_mode
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* register.
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*
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* note: WRREC(Twr) and WRTORD(Twtr) are not in SPD,
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* use conservative value here.
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*/
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ddr->timing_cfg_1 =
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(((picos_to_clk(spd.trp * 250) & 0x07) << 28 ) |
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((picos_to_clk(spd.tras * 1000) & 0x0f ) << 24 ) |
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((picos_to_clk(spd.trcd * 250) & 0x07) << 20 ) |
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((caslat & 0x07) << 16 ) |
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(((picos_to_clk(spd.sset[6] * 1000) - 8) & 0x0f) << 12 ) |
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( 0x300 ) |
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((picos_to_clk(spd.trrd * 250) & 0x07) << 4) | 1);
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ddr->timing_cfg_2 = 0x00000800;
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debug("DDR:timing_cfg_1=0x%08x\n", ddr->timing_cfg_1);
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debug("DDR:timing_cfg_2=0x%08x\n", ddr->timing_cfg_2);
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/*
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* Only DDR I is supported
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* DDR I and II have different mode-register-set definition
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*/
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/* burst length is always 4 */
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switch(caslat) {
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case 2:
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ddr->sdram_mode = 0x52; /* 1.5 */
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break;
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case 3:
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ddr->sdram_mode = 0x22; /* 2.0 */
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break;
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case 4:
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ddr->sdram_mode = 0x62; /* 2.5 */
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break;
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case 5:
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ddr->sdram_mode = 0x32; /* 3.0 */
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break;
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default:
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puts("DDR:only CAS Latency 1.5, 2.0, 2.5, 3.0 is supported.\n");
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return 0;
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}
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debug("DDR:sdram_mode=0x%08x\n", ddr->sdram_mode);
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switch(spd.refresh) {
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case 0x00:
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case 0x80:
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tmp = picos_to_clk(15625000);
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break;
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case 0x01:
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case 0x81:
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tmp = picos_to_clk(3900000);
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break;
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case 0x02:
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case 0x82:
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tmp = picos_to_clk(7800000);
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break;
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case 0x03:
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case 0x83:
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tmp = picos_to_clk(31300000);
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break;
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case 0x04:
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case 0x84:
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tmp = picos_to_clk(62500000);
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break;
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case 0x05:
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case 0x85:
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tmp = picos_to_clk(125000000);
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break;
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default:
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tmp = 0x512;
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break;
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}
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/*
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* Set BSTOPRE to 0x100 for page mode
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* If auto-charge is used, set BSTOPRE = 0
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*/
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ddr->sdram_interval = ((tmp & 0x3fff) << 16) | 0x100;
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debug("DDR:sdram_interval=0x%08x\n", ddr->sdram_interval);
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/*
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* Is this an ECC DDR chip?
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*/
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#if defined(CONFIG_DDR_ECC)
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if (spd.config == 0x02) {
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ddr->err_disable = 0x0000000d;
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ddr->err_sbe = 0x00ff0000;
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}
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debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
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debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
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#endif
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asm("sync;isync;msync");
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udelay(500);
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#ifdef MPC85xx_DDR_SDRAM_CLK_CNTL
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/* Setup the clock control (8555 and later)
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* SDRAM_CLK_CNTL[0] = Source synchronous enable == 1
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* SDRAM_CLK_CNTL[5-7] = Clock Adjust == 3 (3/4 cycle late)
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*/
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ddr->sdram_clk_cntl = 0x83000000;
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#endif
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/*
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* Figure out the settings for the sdram_cfg register. Build up
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* the entire register in 'tmp' before writing since the write into
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* the register will actually enable the memory controller, and all
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* settings must be done before enabling.
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*
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* sdram_cfg[0] = 1 (ddr sdram logic enable)
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* sdram_cfg[1] = 1 (self-refresh-enable)
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* sdram_cfg[6:7] = 2 (SDRAM type = DDR SDRAM)
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*/
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tmp = 0xc2000000;
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/*
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* sdram_cfg[3] = RD_EN - registered DIMM enable
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* A value of 0x26 indicates micron registered DIMMS (micron.com)
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*/
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if (spd.mod_attr == 0x26) {
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tmp |= 0x10000000;
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}
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#if defined(CONFIG_DDR_ECC)
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/*
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* If the user wanted ECC (enabled via sdram_cfg[2])
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*/
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if (spd.config == 0x02) {
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tmp |= 0x20000000;
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}
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#endif
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/*
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* REV1 uses 1T timing.
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* REV2 may use 1T or 2T as configured by the user.
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*/
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{
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uint pvr = get_pvr();
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if (pvr != PVR_85xx_REV1) {
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#if defined(CONFIG_DDR_2T_TIMING)
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/*
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* Enable 2T timing by setting sdram_cfg[16].
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*/
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tmp |= 0x8000;
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#endif
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}
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}
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ddr->sdram_cfg = tmp;
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asm("sync;isync;msync");
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udelay(500);
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debug("DDR:sdram_cfg=0x%08x\n", ddr->sdram_cfg);
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return memsize * 1024 * 1024;
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}
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#endif /* CONFIG_SPD_EEPROM */
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#if defined(CONFIG_DDR_ECC)
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/*
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* Initialize all of memory for ECC, then enable errors.
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*/
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void
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ddr_enable_ecc(unsigned int dram_size)
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{
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uint *p = 0;
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uint i = 0;
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile ccsr_ddr_t *ddr= &immap->im_ddr;
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dma_init();
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for (*p = 0; p < (uint *)(8 * 1024); p++) {
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if (((unsigned int)p & 0x1f) == 0) {
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ppcDcbz((unsigned long) p);
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}
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*p = (unsigned int)0xdeadbeef;
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if (((unsigned int)p & 0x1c) == 0x1c) {
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ppcDcbf((unsigned long) p);
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}
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}
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/* 8K */
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dma_xfer((uint *)0x2000, 0x2000, (uint *)0);
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/* 16K */
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dma_xfer((uint *)0x4000, 0x4000, (uint *)0);
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/* 32K */
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dma_xfer((uint *)0x8000, 0x8000, (uint *)0);
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/* 64K */
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dma_xfer((uint *)0x10000, 0x10000, (uint *)0);
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/* 128k */
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dma_xfer((uint *)0x20000, 0x20000, (uint *)0);
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/* 256k */
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dma_xfer((uint *)0x40000, 0x40000, (uint *)0);
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/* 512k */
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dma_xfer((uint *)0x80000, 0x80000, (uint *)0);
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/* 1M */
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dma_xfer((uint *)0x100000, 0x100000, (uint *)0);
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/* 2M */
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dma_xfer((uint *)0x200000, 0x200000, (uint *)0);
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/* 4M */
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dma_xfer((uint *)0x400000, 0x400000, (uint *)0);
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for (i = 1; i < dram_size / 0x800000; i++) {
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dma_xfer((uint *)(0x800000*i), 0x800000, (uint *)0);
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}
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/*
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* Enable errors for ECC.
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*/
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ddr->err_disable = 0x00000000;
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asm("sync;isync;msync");
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}
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#endif /* CONFIG_DDR_ECC */
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