mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-08 05:43:21 +09:00
7bb75023a7
The driver adds the support for the STMicroelectronics FMC2 NAND Controller found on STM32MP SOCs. This patch adds the polling mode, a basic mode that do not need any DMA channels. Only NAND_ECC_HW mode is actually supported. The driver supports a maximum 8k page size. The following ECC strength and step size are currently supported: - nand-ecc-strength = <8>, nand-ecc-step-size = <512> (BCH8) - nand-ecc-strength = <4>, nand-ecc-step-size = <512> (BCH4) - nand-ecc-strength = <1>, nand-ecc-step-size = <512> (Extended ECC based on Hamming) This patch has been tested on Micron MT29F8G08ABACAH4. Signed-off-by: Christophe Kerello <christophe.kerello@st.com>
79 lines
2.3 KiB
Makefile
79 lines
2.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_NAND_DRIVERS
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NORMAL_DRIVERS=y
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endif
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obj-$(CONFIG_SPL_NAND_AM33XX_BCH) += am335x_spl_bch.o
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obj-$(CONFIG_SPL_NAND_DENALI) += denali_spl.o
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obj-$(CONFIG_SPL_NAND_SIMPLE) += nand_spl_simple.o
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obj-$(CONFIG_SPL_NAND_LOAD) += nand_spl_load.o
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obj-$(CONFIG_SPL_NAND_ECC) += nand_ecc.o
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obj-$(CONFIG_SPL_NAND_BASE) += nand_base.o
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obj-$(CONFIG_SPL_NAND_IDENT) += nand_ids.o nand_timings.o
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obj-$(CONFIG_SPL_NAND_INIT) += nand.o
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ifeq ($(CONFIG_SPL_ENV_SUPPORT),y)
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obj-$(CONFIG_ENV_IS_IN_NAND) += nand_util.o
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endif
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else # not spl
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NORMAL_DRIVERS=y
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obj-y += nand.o
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obj-y += nand_bbt.o
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obj-y += nand_ids.o
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obj-y += nand_util.o
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obj-y += nand_ecc.o
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obj-y += nand_base.o
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obj-y += nand_timings.o
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endif # not spl
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ifdef NORMAL_DRIVERS
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obj-$(CONFIG_NAND_ECC_BCH) += nand_bch.o
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obj-$(CONFIG_NAND_ATMEL) += atmel_nand.o
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obj-$(CONFIG_NAND_ARASAN) += arasan_nfc.o
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obj-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
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obj-$(CONFIG_NAND_DENALI) += denali.o
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obj-$(CONFIG_NAND_DENALI_DT) += denali_dt.o
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obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
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obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
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obj-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
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obj-$(CONFIG_NAND_FSMC) += fsmc_nand.o
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obj-$(CONFIG_NAND_KB9202) += kb9202_nand.o
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obj-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
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obj-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
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obj-$(CONFIG_NAND_LPC32XX_MLC) += lpc32xx_nand_mlc.o
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obj-$(CONFIG_NAND_LPC32XX_SLC) += lpc32xx_nand_slc.o
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obj-$(CONFIG_NAND_VF610_NFC) += vf610_nfc.o
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obj-$(CONFIG_NAND_MXC) += mxc_nand.o
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obj-$(CONFIG_NAND_MXS) += mxs_nand.o
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obj-$(CONFIG_NAND_MXS_DT) += mxs_nand_dt.o
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obj-$(CONFIG_NAND_PXA3XX) += pxa3xx_nand.o
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obj-$(CONFIG_NAND_SPEAR) += spr_nand.o
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obj-$(CONFIG_TEGRA_NAND) += tegra_nand.o
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obj-$(CONFIG_NAND_OMAP_GPMC) += omap_gpmc.o
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obj-$(CONFIG_NAND_OMAP_ELM) += omap_elm.o
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obj-$(CONFIG_NAND_PLAT) += nand_plat.o
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obj-$(CONFIG_NAND_SUNXI) += sunxi_nand.o
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obj-$(CONFIG_NAND_ZYNQ) += zynq_nand.o
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obj-$(CONFIG_NAND_STM32_FMC2) += stm32_fmc2_nand.o
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else # minimal SPL drivers
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obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
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obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
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obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
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obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
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obj-$(CONFIG_NAND_SUNXI) += sunxi_nand_spl.o
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endif # drivers
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