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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-22 19:09:43 +09:00
8a8f084e4f
This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
300 lines
5.6 KiB
C
300 lines
5.6 KiB
C
/*
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* mux.c
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*
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* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <asm/arch/common_def.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#define MUX_CFG(value, offset) \
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__raw_writel(value, (CTRL_BASE + offset));
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/* PAD Control Fields */
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#define SLEWCTRL (0x1 << 6)
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#define RXACTIVE (0x1 << 5)
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#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */
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#define PULLUDEN (0x0 << 3) /* Pull up enabled */
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#define PULLUDDIS (0x1 << 3) /* Pull up disabled */
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#define MODE(val) val /* used for Readability */
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/*
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* PAD CONTROL OFFSETS
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* Field names corresponds to the pad signal name
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*/
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struct pad_signals {
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int gpmc_ad0;
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int gpmc_ad1;
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int gpmc_ad2;
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int gpmc_ad3;
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int gpmc_ad4;
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int gpmc_ad5;
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int gpmc_ad6;
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int gpmc_ad7;
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int gpmc_ad8;
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int gpmc_ad9;
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int gpmc_ad10;
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int gpmc_ad11;
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int gpmc_ad12;
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int gpmc_ad13;
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int gpmc_ad14;
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int gpmc_ad15;
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int gpmc_a0;
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int gpmc_a1;
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int gpmc_a2;
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int gpmc_a3;
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int gpmc_a4;
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int gpmc_a5;
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int gpmc_a6;
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int gpmc_a7;
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int gpmc_a8;
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int gpmc_a9;
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int gpmc_a10;
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int gpmc_a11;
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int gpmc_wait0;
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int gpmc_wpn;
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int gpmc_be1n;
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int gpmc_csn0;
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int gpmc_csn1;
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int gpmc_csn2;
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int gpmc_csn3;
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int gpmc_clk;
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int gpmc_advn_ale;
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int gpmc_oen_ren;
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int gpmc_wen;
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int gpmc_be0n_cle;
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int lcd_data0;
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int lcd_data1;
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int lcd_data2;
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int lcd_data3;
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int lcd_data4;
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int lcd_data5;
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int lcd_data6;
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int lcd_data7;
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int lcd_data8;
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int lcd_data9;
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int lcd_data10;
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int lcd_data11;
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int lcd_data12;
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int lcd_data13;
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int lcd_data14;
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int lcd_data15;
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int lcd_vsync;
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int lcd_hsync;
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int lcd_pclk;
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int lcd_ac_bias_en;
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int mmc0_dat3;
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int mmc0_dat2;
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int mmc0_dat1;
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int mmc0_dat0;
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int mmc0_clk;
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int mmc0_cmd;
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int mii1_col;
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int mii1_crs;
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int mii1_rxerr;
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int mii1_txen;
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int mii1_rxdv;
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int mii1_txd3;
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int mii1_txd2;
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int mii1_txd1;
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int mii1_txd0;
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int mii1_txclk;
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int mii1_rxclk;
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int mii1_rxd3;
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int mii1_rxd2;
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int mii1_rxd1;
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int mii1_rxd0;
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int rmii1_refclk;
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int mdio_data;
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int mdio_clk;
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int spi0_sclk;
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int spi0_d0;
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int spi0_d1;
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int spi0_cs0;
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int spi0_cs1;
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int ecap0_in_pwm0_out;
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int uart0_ctsn;
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int uart0_rtsn;
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int uart0_rxd;
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int uart0_txd;
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int uart1_ctsn;
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int uart1_rtsn;
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int uart1_rxd;
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int uart1_txd;
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int i2c0_sda;
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int i2c0_scl;
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int mcasp0_aclkx;
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int mcasp0_fsx;
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int mcasp0_axr0;
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int mcasp0_ahclkr;
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int mcasp0_aclkr;
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int mcasp0_fsr;
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int mcasp0_axr1;
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int mcasp0_ahclkx;
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int xdma_event_intr0;
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int xdma_event_intr1;
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int nresetin_out;
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int porz;
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int nnmi;
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int osc0_in;
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int osc0_out;
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int rsvd1;
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int tms;
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int tdi;
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int tdo;
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int tck;
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int ntrst;
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int emu0;
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int emu1;
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int osc1_in;
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int osc1_out;
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int pmic_power_en;
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int rtc_porz;
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int rsvd2;
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int ext_wakeup;
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int enz_kaldo_1p8v;
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int usb0_dm;
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int usb0_dp;
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int usb0_ce;
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int usb0_id;
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int usb0_vbus;
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int usb0_drvvbus;
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int usb1_dm;
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int usb1_dp;
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int usb1_ce;
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int usb1_id;
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int usb1_vbus;
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int usb1_drvvbus;
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int ddr_resetn;
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int ddr_csn0;
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int ddr_cke;
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int ddr_ck;
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int ddr_nck;
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int ddr_casn;
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int ddr_rasn;
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int ddr_wen;
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int ddr_ba0;
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int ddr_ba1;
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int ddr_ba2;
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int ddr_a0;
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int ddr_a1;
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int ddr_a2;
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int ddr_a3;
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int ddr_a4;
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int ddr_a5;
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int ddr_a6;
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int ddr_a7;
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int ddr_a8;
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int ddr_a9;
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int ddr_a10;
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int ddr_a11;
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int ddr_a12;
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int ddr_a13;
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int ddr_a14;
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int ddr_a15;
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int ddr_odt;
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int ddr_d0;
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int ddr_d1;
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int ddr_d2;
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int ddr_d3;
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int ddr_d4;
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int ddr_d5;
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int ddr_d6;
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int ddr_d7;
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int ddr_d8;
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int ddr_d9;
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int ddr_d10;
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int ddr_d11;
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int ddr_d12;
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int ddr_d13;
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int ddr_d14;
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int ddr_d15;
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int ddr_dqm0;
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int ddr_dqm1;
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int ddr_dqs0;
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int ddr_dqsn0;
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int ddr_dqs1;
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int ddr_dqsn1;
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int ddr_vref;
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int ddr_vtp;
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int ddr_strben0;
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int ddr_strben1;
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int ain7;
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int ain6;
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int ain5;
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int ain4;
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int ain3;
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int ain2;
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int ain1;
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int ain0;
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int vrefp;
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int vrefn;
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};
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struct module_pin_mux {
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short reg_offset;
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unsigned char val;
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};
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/* Pad control register offset */
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#define PAD_CTRL_BASE 0x800
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#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \
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(PAD_CTRL_BASE))->x)
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static struct module_pin_mux uart0_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
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{-1},
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};
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc0_pin_mux[] = {
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{OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */
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{OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */
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{OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mcasp0_aclkr), (MODE(4) | RXACTIVE)}, /* MMC0_WP */
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{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */
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{-1},
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};
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#endif
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/*
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* Configure the pin mux for the module
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*/
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static void configure_module_pin_mux(struct module_pin_mux *mod_pin_mux)
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{
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int i;
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if (!mod_pin_mux)
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return;
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for (i = 0; mod_pin_mux[i].reg_offset != -1; i++)
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MUX_CFG(mod_pin_mux[i].val, mod_pin_mux[i].reg_offset);
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}
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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#ifdef CONFIG_MMC
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void enable_mmc0_pin_mux(void)
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{
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configure_module_pin_mux(mmc0_pin_mux);
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}
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#endif
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