mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
8a73bef338
The R-Car3 SDHI should set these two bits in DMA_MODE register according to the specification, to indicate 64bit bus width. No other bus width options are permitted and the default value is 0, which is incorrect. Set the bits accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
783 lines
19 KiB
C
783 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <cpu_func.h>
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#include <fdtdec.h>
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#include <mmc.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <dm/pinctrl.h>
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#include <linux/compat.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <power/regulator.h>
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#include <asm/unaligned.h>
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#include "tmio-common.h"
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DECLARE_GLOBAL_DATA_PTR;
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static u64 tmio_sd_readq(struct tmio_sd_priv *priv, unsigned int reg)
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{
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return readq(priv->regbase + (reg << 1));
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}
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static void tmio_sd_writeq(struct tmio_sd_priv *priv,
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u64 val, unsigned int reg)
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{
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writeq(val, priv->regbase + (reg << 1));
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}
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static u16 tmio_sd_readw(struct tmio_sd_priv *priv, unsigned int reg)
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{
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return readw(priv->regbase + (reg >> 1));
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}
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static void tmio_sd_writew(struct tmio_sd_priv *priv,
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u16 val, unsigned int reg)
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{
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writew(val, priv->regbase + (reg >> 1));
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}
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u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg)
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{
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u32 val;
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if (priv->caps & TMIO_SD_CAP_64BIT)
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return readl(priv->regbase + (reg << 1));
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else if (priv->caps & TMIO_SD_CAP_16BIT) {
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val = readw(priv->regbase + (reg >> 1)) & 0xffff;
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if ((reg == TMIO_SD_RSP10) || (reg == TMIO_SD_RSP32) ||
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(reg == TMIO_SD_RSP54) || (reg == TMIO_SD_RSP76)) {
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val |= readw(priv->regbase + (reg >> 1) + 2) << 16;
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}
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return val;
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} else
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return readl(priv->regbase + reg);
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}
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void tmio_sd_writel(struct tmio_sd_priv *priv,
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u32 val, unsigned int reg)
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{
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if (priv->caps & TMIO_SD_CAP_64BIT)
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writel(val, priv->regbase + (reg << 1));
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else if (priv->caps & TMIO_SD_CAP_16BIT) {
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writew(val & 0xffff, priv->regbase + (reg >> 1));
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if (reg == TMIO_SD_INFO1 || reg == TMIO_SD_INFO1_MASK ||
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reg == TMIO_SD_INFO2 || reg == TMIO_SD_INFO2_MASK ||
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reg == TMIO_SD_ARG)
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writew(val >> 16, priv->regbase + (reg >> 1) + 2);
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} else
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writel(val, priv->regbase + reg);
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}
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static int tmio_sd_check_error(struct udevice *dev, struct mmc_cmd *cmd)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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u32 info2 = tmio_sd_readl(priv, TMIO_SD_INFO2);
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if (info2 & TMIO_SD_INFO2_ERR_RTO) {
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/*
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* TIMEOUT must be returned for unsupported command. Do not
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* display error log since this might be a part of sequence to
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* distinguish between SD and MMC.
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*/
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return -ETIMEDOUT;
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}
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if (info2 & TMIO_SD_INFO2_ERR_TO) {
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dev_err(dev, "timeout error\n");
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return -ETIMEDOUT;
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}
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if (info2 & (TMIO_SD_INFO2_ERR_END | TMIO_SD_INFO2_ERR_CRC |
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TMIO_SD_INFO2_ERR_IDX)) {
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if ((cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK) &&
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(cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200))
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dev_err(dev, "communication out of sync\n");
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return -EILSEQ;
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}
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if (info2 & (TMIO_SD_INFO2_ERR_ILA | TMIO_SD_INFO2_ERR_ILR |
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TMIO_SD_INFO2_ERR_ILW)) {
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dev_err(dev, "illegal access\n");
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return -EIO;
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}
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return 0;
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}
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static int tmio_sd_wait_for_irq(struct udevice *dev, struct mmc_cmd *cmd,
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unsigned int reg, u32 flag)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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long wait = 1000000;
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int ret;
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while (!(tmio_sd_readl(priv, reg) & flag)) {
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if (wait-- < 0) {
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dev_err(dev, "timeout\n");
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return -ETIMEDOUT;
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}
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ret = tmio_sd_check_error(dev, cmd);
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if (ret)
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return ret;
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udelay(1);
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}
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return 0;
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}
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#define tmio_pio_read_fifo(__width, __suffix) \
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static void tmio_pio_read_fifo_##__width(struct tmio_sd_priv *priv, \
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char *pbuf, uint blksz) \
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{ \
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u##__width *buf = (u##__width *)pbuf; \
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int i; \
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\
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if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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*buf++ = tmio_sd_read##__suffix(priv, \
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TMIO_SD_BUF); \
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} \
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} else { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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u##__width data; \
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data = tmio_sd_read##__suffix(priv, \
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TMIO_SD_BUF); \
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put_unaligned(data, buf++); \
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} \
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} \
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}
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tmio_pio_read_fifo(64, q)
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tmio_pio_read_fifo(32, l)
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tmio_pio_read_fifo(16, w)
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static int tmio_sd_pio_read_one_block(struct udevice *dev, struct mmc_cmd *cmd,
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char *pbuf, uint blocksize)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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int ret;
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/* wait until the buffer is filled with data */
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ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
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TMIO_SD_INFO2_BRE);
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if (ret)
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return ret;
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/*
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* Clear the status flag _before_ read the buffer out because
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* TMIO_SD_INFO2_BRE is edge-triggered, not level-triggered.
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*/
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tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
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if (priv->caps & TMIO_SD_CAP_64BIT)
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tmio_pio_read_fifo_64(priv, pbuf, blocksize);
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else if (priv->caps & TMIO_SD_CAP_16BIT)
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tmio_pio_read_fifo_16(priv, pbuf, blocksize);
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else
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tmio_pio_read_fifo_32(priv, pbuf, blocksize);
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return 0;
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}
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#define tmio_pio_write_fifo(__width, __suffix) \
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static void tmio_pio_write_fifo_##__width(struct tmio_sd_priv *priv, \
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const char *pbuf, uint blksz)\
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{ \
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const u##__width *buf = (const u##__width *)pbuf; \
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int i; \
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\
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if (likely(IS_ALIGNED((uintptr_t)buf, ((__width) / 8)))) { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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tmio_sd_write##__suffix(priv, *buf++, \
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TMIO_SD_BUF); \
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} \
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} else { \
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for (i = 0; i < blksz / ((__width) / 8); i++) { \
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u##__width data = get_unaligned(buf++); \
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tmio_sd_write##__suffix(priv, data, \
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TMIO_SD_BUF); \
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} \
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} \
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}
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tmio_pio_write_fifo(64, q)
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tmio_pio_write_fifo(32, l)
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tmio_pio_write_fifo(16, w)
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static int tmio_sd_pio_write_one_block(struct udevice *dev, struct mmc_cmd *cmd,
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const char *pbuf, uint blocksize)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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int ret;
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/* wait until the buffer becomes empty */
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ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
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TMIO_SD_INFO2_BWE);
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if (ret)
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return ret;
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tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
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if (priv->caps & TMIO_SD_CAP_64BIT)
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tmio_pio_write_fifo_64(priv, pbuf, blocksize);
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else if (priv->caps & TMIO_SD_CAP_16BIT)
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tmio_pio_write_fifo_16(priv, pbuf, blocksize);
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else
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tmio_pio_write_fifo_32(priv, pbuf, blocksize);
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return 0;
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}
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static int tmio_sd_pio_xfer(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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const char *src = data->src;
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char *dest = data->dest;
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int i, ret;
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for (i = 0; i < data->blocks; i++) {
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if (data->flags & MMC_DATA_READ)
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ret = tmio_sd_pio_read_one_block(dev, cmd, dest,
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data->blocksize);
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else
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ret = tmio_sd_pio_write_one_block(dev, cmd, src,
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data->blocksize);
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if (ret)
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return ret;
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if (data->flags & MMC_DATA_READ)
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dest += data->blocksize;
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else
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src += data->blocksize;
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}
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return 0;
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}
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static void tmio_sd_dma_start(struct tmio_sd_priv *priv,
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dma_addr_t dma_addr)
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{
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u32 tmp;
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tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO1);
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tmio_sd_writel(priv, 0, TMIO_SD_DMA_INFO2);
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/* enable DMA */
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tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
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tmp |= TMIO_SD_EXTMODE_DMA_EN;
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tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
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tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_L);
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/* suppress the warning "right shift count >= width of type" */
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dma_addr >>= min_t(int, 32, 8 * sizeof(dma_addr));
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tmio_sd_writel(priv, dma_addr & U32_MAX, TMIO_SD_DMA_ADDR_H);
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tmio_sd_writel(priv, TMIO_SD_DMA_CTL_START, TMIO_SD_DMA_CTL);
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}
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static int tmio_sd_dma_wait_for_irq(struct udevice *dev, u32 flag,
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unsigned int blocks)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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long wait = 1000000 + 10 * blocks;
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while (!(tmio_sd_readl(priv, TMIO_SD_DMA_INFO1) & flag)) {
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if (wait-- < 0) {
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dev_err(dev, "timeout during DMA\n");
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return -ETIMEDOUT;
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}
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udelay(10);
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}
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if (tmio_sd_readl(priv, TMIO_SD_DMA_INFO2)) {
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dev_err(dev, "error during DMA\n");
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return -EIO;
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}
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return 0;
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}
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static int tmio_sd_dma_xfer(struct udevice *dev, struct mmc_data *data)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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size_t len = data->blocks * data->blocksize;
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void *buf;
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enum dma_data_direction dir;
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dma_addr_t dma_addr;
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u32 poll_flag, tmp;
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int ret;
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tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
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tmp |= priv->idma_bus_width;
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if (data->flags & MMC_DATA_READ) {
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buf = data->dest;
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dir = DMA_FROM_DEVICE;
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/*
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* The DMA READ completion flag position differs on Socionext
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* and Renesas SoCs. It is bit 20 on Socionext SoCs and using
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* bit 17 is a hardware bug and forbidden. It is either bit 17
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* or bit 20 on Renesas SoCs, depending on SoC.
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*/
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poll_flag = priv->read_poll_flag;
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tmp |= TMIO_SD_DMA_MODE_DIR_RD;
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} else {
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buf = (void *)data->src;
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dir = DMA_TO_DEVICE;
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poll_flag = TMIO_SD_DMA_INFO1_END_WR;
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tmp &= ~TMIO_SD_DMA_MODE_DIR_RD;
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}
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tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
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dma_addr = dma_map_single(buf, len, dir);
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tmio_sd_dma_start(priv, dma_addr);
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ret = tmio_sd_dma_wait_for_irq(dev, poll_flag, data->blocks);
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if (poll_flag == TMIO_SD_DMA_INFO1_END_RD)
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udelay(1);
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dma_unmap_single(dma_addr, len, dir);
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return ret;
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}
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/* check if the address is DMA'able */
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static bool tmio_sd_addr_is_dmaable(struct mmc_data *data)
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{
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uintptr_t addr = (uintptr_t)data->src;
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if (!IS_ALIGNED(addr, TMIO_SD_DMA_MINALIGN))
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return false;
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#if defined(CONFIG_RCAR_GEN3)
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if (!(data->flags & MMC_DATA_READ) && !IS_ALIGNED(addr, 128))
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return false;
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/* Gen3 DMA has 32bit limit */
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if (addr >> 32)
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return false;
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#endif
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#if defined(CONFIG_ARCH_UNIPHIER) && !defined(CONFIG_ARM64) && \
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defined(CONFIG_SPL_BUILD)
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/*
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* For UniPhier ARMv7 SoCs, the stack is allocated in the locked ways
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* of L2, which is unreachable from the DMA engine.
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*/
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if (addr < CONFIG_SPL_STACK)
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return false;
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#endif
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return true;
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}
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int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct tmio_sd_priv *priv = dev_get_priv(dev);
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int ret;
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u32 tmp;
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if (tmio_sd_readl(priv, TMIO_SD_INFO2) & TMIO_SD_INFO2_CBSY) {
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dev_err(dev, "command busy\n");
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return -EBUSY;
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}
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/* clear all status flags */
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tmio_sd_writel(priv, 0, TMIO_SD_INFO1);
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tmio_sd_writel(priv, 0, TMIO_SD_INFO2);
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/* disable DMA once */
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tmp = tmio_sd_readl(priv, TMIO_SD_EXTMODE);
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tmp &= ~TMIO_SD_EXTMODE_DMA_EN;
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tmio_sd_writel(priv, tmp, TMIO_SD_EXTMODE);
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tmio_sd_writel(priv, cmd->cmdarg, TMIO_SD_ARG);
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tmp = cmd->cmdidx;
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if (data) {
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tmio_sd_writel(priv, data->blocksize, TMIO_SD_SIZE);
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tmio_sd_writel(priv, data->blocks, TMIO_SD_SECCNT);
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/* Do not send CMD12 automatically */
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tmp |= TMIO_SD_CMD_NOSTOP | TMIO_SD_CMD_DATA;
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if (data->blocks > 1)
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tmp |= TMIO_SD_CMD_MULTI;
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if (data->flags & MMC_DATA_READ)
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tmp |= TMIO_SD_CMD_RD;
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}
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/*
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* Do not use the response type auto-detection on this hardware.
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* CMD8, for example, has different response types on SD and eMMC,
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* while this controller always assumes the response type for SD.
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* Set the response type manually.
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*/
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switch (cmd->resp_type) {
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case MMC_RSP_NONE:
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tmp |= TMIO_SD_CMD_RSP_NONE;
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break;
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case MMC_RSP_R1:
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tmp |= TMIO_SD_CMD_RSP_R1;
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break;
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case MMC_RSP_R1b:
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tmp |= TMIO_SD_CMD_RSP_R1B;
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break;
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case MMC_RSP_R2:
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tmp |= TMIO_SD_CMD_RSP_R2;
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break;
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case MMC_RSP_R3:
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tmp |= TMIO_SD_CMD_RSP_R3;
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break;
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default:
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dev_err(dev, "unknown response type\n");
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return -EINVAL;
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}
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dev_dbg(dev, "sending CMD%d (SD_CMD=%08x, SD_ARG=%08x)\n",
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cmd->cmdidx, tmp, cmd->cmdarg);
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tmio_sd_writel(priv, tmp, TMIO_SD_CMD);
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ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
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TMIO_SD_INFO1_RSP);
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if (ret)
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return ret;
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if (cmd->resp_type & MMC_RSP_136) {
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u32 rsp_127_104 = tmio_sd_readl(priv, TMIO_SD_RSP76);
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u32 rsp_103_72 = tmio_sd_readl(priv, TMIO_SD_RSP54);
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u32 rsp_71_40 = tmio_sd_readl(priv, TMIO_SD_RSP32);
|
|
u32 rsp_39_8 = tmio_sd_readl(priv, TMIO_SD_RSP10);
|
|
|
|
cmd->response[0] = ((rsp_127_104 & 0x00ffffff) << 8) |
|
|
((rsp_103_72 & 0xff000000) >> 24);
|
|
cmd->response[1] = ((rsp_103_72 & 0x00ffffff) << 8) |
|
|
((rsp_71_40 & 0xff000000) >> 24);
|
|
cmd->response[2] = ((rsp_71_40 & 0x00ffffff) << 8) |
|
|
((rsp_39_8 & 0xff000000) >> 24);
|
|
cmd->response[3] = (rsp_39_8 & 0xffffff) << 8;
|
|
} else {
|
|
/* bit 39-8 */
|
|
cmd->response[0] = tmio_sd_readl(priv, TMIO_SD_RSP10);
|
|
}
|
|
|
|
if (data) {
|
|
/* use DMA if the HW supports it and the buffer is aligned */
|
|
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL &&
|
|
tmio_sd_addr_is_dmaable(data))
|
|
ret = tmio_sd_dma_xfer(dev, data);
|
|
else
|
|
ret = tmio_sd_pio_xfer(dev, cmd, data);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO1,
|
|
TMIO_SD_INFO1_CMP);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return tmio_sd_wait_for_irq(dev, cmd, TMIO_SD_INFO2,
|
|
TMIO_SD_INFO2_SCLKDIVEN);
|
|
}
|
|
|
|
static int tmio_sd_set_bus_width(struct tmio_sd_priv *priv,
|
|
struct mmc *mmc)
|
|
{
|
|
u32 val, tmp;
|
|
|
|
switch (mmc->bus_width) {
|
|
case 0:
|
|
case 1:
|
|
val = TMIO_SD_OPTION_WIDTH_1;
|
|
break;
|
|
case 4:
|
|
val = TMIO_SD_OPTION_WIDTH_4;
|
|
break;
|
|
case 8:
|
|
val = TMIO_SD_OPTION_WIDTH_8;
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
tmp = tmio_sd_readl(priv, TMIO_SD_OPTION);
|
|
tmp &= ~TMIO_SD_OPTION_WIDTH_MASK;
|
|
tmp |= val;
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_OPTION);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void tmio_sd_set_ddr_mode(struct tmio_sd_priv *priv,
|
|
struct mmc *mmc)
|
|
{
|
|
u32 tmp;
|
|
|
|
tmp = tmio_sd_readl(priv, TMIO_SD_IF_MODE);
|
|
if (mmc->ddr_mode)
|
|
tmp |= TMIO_SD_IF_MODE_DDR;
|
|
else
|
|
tmp &= ~TMIO_SD_IF_MODE_DDR;
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_IF_MODE);
|
|
}
|
|
|
|
static ulong tmio_sd_clk_get_rate(struct tmio_sd_priv *priv)
|
|
{
|
|
return priv->clk_get_rate(priv);
|
|
}
|
|
|
|
static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv, struct mmc *mmc)
|
|
{
|
|
unsigned int divisor;
|
|
u32 tmp, val = 0;
|
|
ulong mclk;
|
|
|
|
if (mmc->clock) {
|
|
mclk = tmio_sd_clk_get_rate(priv);
|
|
|
|
divisor = DIV_ROUND_UP(mclk, mmc->clock);
|
|
|
|
/* Do not set divider to 0xff in DDR mode */
|
|
if (mmc->ddr_mode && (divisor == 1))
|
|
divisor = 2;
|
|
|
|
if (divisor <= 1)
|
|
val = (priv->caps & TMIO_SD_CAP_RCAR) ?
|
|
TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;
|
|
else if (divisor <= 2)
|
|
val = TMIO_SD_CLKCTL_DIV2;
|
|
else if (divisor <= 4)
|
|
val = TMIO_SD_CLKCTL_DIV4;
|
|
else if (divisor <= 8)
|
|
val = TMIO_SD_CLKCTL_DIV8;
|
|
else if (divisor <= 16)
|
|
val = TMIO_SD_CLKCTL_DIV16;
|
|
else if (divisor <= 32)
|
|
val = TMIO_SD_CLKCTL_DIV32;
|
|
else if (divisor <= 64)
|
|
val = TMIO_SD_CLKCTL_DIV64;
|
|
else if (divisor <= 128)
|
|
val = TMIO_SD_CLKCTL_DIV128;
|
|
else if (divisor <= 256)
|
|
val = TMIO_SD_CLKCTL_DIV256;
|
|
else if (divisor <= 512 || !(priv->caps & TMIO_SD_CAP_DIV1024))
|
|
val = TMIO_SD_CLKCTL_DIV512;
|
|
else
|
|
val = TMIO_SD_CLKCTL_DIV1024;
|
|
}
|
|
|
|
tmp = tmio_sd_readl(priv, TMIO_SD_CLKCTL);
|
|
if (mmc->clock &&
|
|
!((tmp & TMIO_SD_CLKCTL_SCLKEN) &&
|
|
((tmp & TMIO_SD_CLKCTL_DIV_MASK) == val))) {
|
|
/*
|
|
* Stop the clock before changing its rate
|
|
* to avoid a glitch signal
|
|
*/
|
|
tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
|
|
|
|
/* Change the clock rate. */
|
|
tmp &= ~TMIO_SD_CLKCTL_DIV_MASK;
|
|
tmp |= val;
|
|
}
|
|
|
|
/* Enable or Disable the clock */
|
|
if (mmc->clk_disable) {
|
|
tmp |= TMIO_SD_CLKCTL_OFFEN;
|
|
tmp &= ~TMIO_SD_CLKCTL_SCLKEN;
|
|
} else {
|
|
tmp &= ~TMIO_SD_CLKCTL_OFFEN;
|
|
tmp |= TMIO_SD_CLKCTL_SCLKEN;
|
|
}
|
|
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_CLKCTL);
|
|
|
|
udelay(1000);
|
|
}
|
|
|
|
static void tmio_sd_set_pins(struct udevice *dev)
|
|
{
|
|
__maybe_unused struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
|
|
#ifdef CONFIG_DM_REGULATOR
|
|
struct tmio_sd_priv *priv = dev_get_priv(dev);
|
|
|
|
if (priv->vqmmc_dev) {
|
|
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
|
|
regulator_set_value(priv->vqmmc_dev, 1800000);
|
|
else
|
|
regulator_set_value(priv->vqmmc_dev, 3300000);
|
|
regulator_set_enable(priv->vqmmc_dev, true);
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_PINCTRL
|
|
if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
|
|
pinctrl_select_state(dev, "state_uhs");
|
|
else
|
|
pinctrl_select_state(dev, "default");
|
|
#endif
|
|
}
|
|
|
|
int tmio_sd_set_ios(struct udevice *dev)
|
|
{
|
|
struct tmio_sd_priv *priv = dev_get_priv(dev);
|
|
struct mmc *mmc = mmc_get_mmc_dev(dev);
|
|
int ret;
|
|
|
|
dev_dbg(dev, "clock %uHz, DDRmode %d, width %u\n",
|
|
mmc->clock, mmc->ddr_mode, mmc->bus_width);
|
|
|
|
tmio_sd_set_clk_rate(priv, mmc);
|
|
ret = tmio_sd_set_bus_width(priv, mmc);
|
|
if (ret)
|
|
return ret;
|
|
tmio_sd_set_ddr_mode(priv, mmc);
|
|
tmio_sd_set_pins(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int tmio_sd_get_cd(struct udevice *dev)
|
|
{
|
|
struct tmio_sd_priv *priv = dev_get_priv(dev);
|
|
|
|
if (priv->caps & TMIO_SD_CAP_NONREMOVABLE)
|
|
return 1;
|
|
|
|
return !!(tmio_sd_readl(priv, TMIO_SD_INFO1) &
|
|
TMIO_SD_INFO1_CD);
|
|
}
|
|
|
|
static void tmio_sd_host_init(struct tmio_sd_priv *priv)
|
|
{
|
|
u32 tmp;
|
|
|
|
/* soft reset of the host */
|
|
tmp = tmio_sd_readl(priv, TMIO_SD_SOFT_RST);
|
|
tmp &= ~TMIO_SD_SOFT_RST_RSTX;
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
|
|
tmp |= TMIO_SD_SOFT_RST_RSTX;
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_SOFT_RST);
|
|
|
|
/* FIXME: implement eMMC hw_reset */
|
|
|
|
tmio_sd_writel(priv, TMIO_SD_STOP_SEC, TMIO_SD_STOP);
|
|
|
|
/*
|
|
* Connected to 32bit AXI.
|
|
* This register dropped backward compatibility at version 0x10.
|
|
* Write an appropriate value depending on the IP version.
|
|
*/
|
|
if (priv->version >= 0x10) {
|
|
if (priv->caps & TMIO_SD_CAP_64BIT)
|
|
tmio_sd_writel(priv, 0x000, TMIO_SD_HOST_MODE);
|
|
else
|
|
tmio_sd_writel(priv, 0x101, TMIO_SD_HOST_MODE);
|
|
} else {
|
|
tmio_sd_writel(priv, 0x0, TMIO_SD_HOST_MODE);
|
|
}
|
|
|
|
if (priv->caps & TMIO_SD_CAP_DMA_INTERNAL) {
|
|
tmp = tmio_sd_readl(priv, TMIO_SD_DMA_MODE);
|
|
tmp |= TMIO_SD_DMA_MODE_ADDR_INC;
|
|
tmp |= priv->idma_bus_width;
|
|
tmio_sd_writel(priv, tmp, TMIO_SD_DMA_MODE);
|
|
}
|
|
}
|
|
|
|
int tmio_sd_bind(struct udevice *dev)
|
|
{
|
|
struct tmio_sd_plat *plat = dev_get_plat(dev);
|
|
|
|
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
|
}
|
|
|
|
int tmio_sd_probe(struct udevice *dev, u32 quirks)
|
|
{
|
|
struct tmio_sd_plat *plat = dev_get_plat(dev);
|
|
struct tmio_sd_priv *priv = dev_get_priv(dev);
|
|
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
|
fdt_addr_t base;
|
|
ulong mclk;
|
|
int ret;
|
|
|
|
base = dev_read_addr(dev);
|
|
if (base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
priv->regbase = devm_ioremap(dev, base, SZ_2K);
|
|
if (!priv->regbase)
|
|
return -ENOMEM;
|
|
|
|
#ifdef CONFIG_DM_REGULATOR
|
|
device_get_supply_regulator(dev, "vqmmc-supply", &priv->vqmmc_dev);
|
|
if (priv->vqmmc_dev)
|
|
regulator_set_value(priv->vqmmc_dev, 3300000);
|
|
#endif
|
|
|
|
ret = mmc_of_parse(dev, &plat->cfg);
|
|
if (ret < 0) {
|
|
dev_err(dev, "failed to parse host caps\n");
|
|
return ret;
|
|
}
|
|
|
|
plat->cfg.name = dev->name;
|
|
plat->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
|
|
|
|
if (quirks)
|
|
priv->caps = quirks;
|
|
|
|
priv->version = tmio_sd_readl(priv, TMIO_SD_VERSION) &
|
|
TMIO_SD_VERSION_IP;
|
|
dev_dbg(dev, "version %x\n", priv->version);
|
|
if (priv->version >= 0x10) {
|
|
priv->caps |= TMIO_SD_CAP_DMA_INTERNAL;
|
|
priv->caps |= TMIO_SD_CAP_DIV1024;
|
|
}
|
|
|
|
if (fdt_get_property(gd->fdt_blob, dev_of_offset(dev), "non-removable",
|
|
NULL))
|
|
priv->caps |= TMIO_SD_CAP_NONREMOVABLE;
|
|
|
|
tmio_sd_host_init(priv);
|
|
|
|
mclk = tmio_sd_clk_get_rate(priv);
|
|
|
|
plat->cfg.voltages = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34;
|
|
plat->cfg.f_min = mclk /
|
|
(priv->caps & TMIO_SD_CAP_DIV1024 ? 1024 : 512);
|
|
plat->cfg.f_max = mclk;
|
|
if (quirks & TMIO_SD_CAP_16BIT)
|
|
plat->cfg.b_max = U16_MAX; /* max value of TMIO_SD_SECCNT */
|
|
else
|
|
plat->cfg.b_max = U32_MAX; /* max value of TMIO_SD_SECCNT */
|
|
|
|
upriv->mmc = &plat->mmc;
|
|
|
|
return 0;
|
|
}
|