mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
7682a99826
Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
189 lines
3.5 KiB
ArmAsm
189 lines
3.5 KiB
ArmAsm
/*
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* Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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/* Change PERCLK1DIV to 14 ie 14+1 */
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ldr r0, =PCDR
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ldr r1, =CONFIG_SYS_PCDR_VAL
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str r1, [r0]
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/* set MCU PLL Control Register 0 */
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ldr r0, =MPCTL0
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ldr r1, =CONFIG_SYS_MPCTL0_VAL
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str r1, [r0]
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/* set mpll restart bit */
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<21)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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/* set System PLL Control Register 0 */
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ldr r0, =SPCTL0
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ldr r1, =CONFIG_SYS_SPCTL0_VAL
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str r1, [r0]
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/* set spll restart bit */
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ldr r0, =CSCR
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ldr r1, [r0]
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orr r1,r1,#(1<<22)
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str r1, [r0]
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mov r2,#0x10
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1:
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mov r3,#0x2000
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2:
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subs r3,r3,#1
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bne 2b
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subs r2,r2,#1
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bne 1b
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ldr r0, =CSCR
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ldr r1, =CONFIG_SYS_CSCR_VAL
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str r1, [r0]
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/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
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*this.....
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*
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* It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
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* register 1, this stops it using the output of the PLL and thus runs at the
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* slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
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* use the value set in the CM_OSC registers...regardless of what you set it
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* too! Thus, although i thought i was running at 140MHz, i'm actually running
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* at 40!..
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* Slapping this into my bootloader does the trick...
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* MRC p15,0,r0,c1,c0,0 ; read core configuration register
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* ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
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* MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
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* register
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*/
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MRC p15,0,r0,c1,c0,0
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ORR r0,r0,#0xC0000000
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MCR p15,0,r0,c1,c0,0
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ldr r0, =GPR(0)
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ldr r1, =CONFIG_SYS_GPR_A_VAL
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str r1, [r0]
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ldr r0, =GIUS(0)
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ldr r1, =CONFIG_SYS_GIUS_A_VAL
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str r1, [r0]
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/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
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ldr r0, =FMCR
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ldr r1, =CONFIG_SYS_FMCR_VAL
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str r1, [r0]
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ldr r0, =CS0U
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ldr r1, =CONFIG_SYS_CS0U_VAL
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str r1, [r0]
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ldr r0, =CS0L
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ldr r1, =CONFIG_SYS_CS0L_VAL
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str r1, [r0]
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ldr r0, =CS1U
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ldr r1, =CONFIG_SYS_CS1U_VAL
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str r1, [r0]
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ldr r0, =CS1L
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ldr r1, =CONFIG_SYS_CS1L_VAL
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str r1, [r0]
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ldr r0, =CS2U
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ldr r1, =CONFIG_SYS_CS2U_VAL
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str r1, [r0]
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ldr r0, =CS2L
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ldr r1, =CONFIG_SYS_CS2L_VAL
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str r1, [r0]
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ldr r0, =CS3U
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ldr r1, =CONFIG_SYS_CS3U_VAL
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str r1, [r0]
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ldr r0, =CS3L
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ldr r1, =CONFIG_SYS_CS3L_VAL
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str r1, [r0]
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ldr r0, =CS4U
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ldr r1, =CONFIG_SYS_CS4U_VAL
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str r1, [r0]
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ldr r0, =CS4L
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ldr r1, =CONFIG_SYS_CS4L_VAL
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str r1, [r0]
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ldr r0, =CS5U
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ldr r1, =CONFIG_SYS_CS5U_VAL
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str r1, [r0]
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ldr r0, =CS5L
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ldr r1, =CONFIG_SYS_CS5L_VAL
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str r1, [r0]
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/* SDRAM Setup */
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ldr r0, =SDCTL0
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ldr r1, =PRECHARGE_CMD
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str r1, [r0]
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ldr r0, =0x08200000
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ldr r1, =0x0 /* Issue Precharge all Command */
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =AUTOREFRESH_CMD
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str r1, [r0]
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ldr r0, =0x08000000
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ldr r1, =0x0 /* Issue AutoRefresh Command */
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =0xb10a8300
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str r1, [r0]
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ldr r0, =0x08223000 /* CAS Latency 2 */
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ldr r1, =0x0 /* Issue Mode Register Command, Burst Length = 8 */
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str r1, [r0]
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ldr r0, =SDCTL0
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ldr r1, =0x810a8200 /* Set to Normal Mode CAS 2 */
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str r1, [r0]
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mov pc,r10
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