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https://github.com/brain-hackers/u-boot-brain
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![Anton Vorontsov](/assets/img/avatar_default.png)
This patch adds support for eSDHC on MPC837XERDB boards. The WP switch doesn't seem to work on RDB boards though, the WP pin is always asserted (can see the pin state when it's in GPIO mode). FSL DR USB and FSL eSDHC are mutually exclusive because of pins multiplexing, so user should specify 'esdhc' or 'dr_usb' options in the hwconfig environment variable to choose between the devices. p.s. Now we're very close to a monitor len limit (196 bytes left using gcc-4.2.0), so also increase the monitor len by one sector (64 KB). Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
218 lines
5.4 KiB
C
218 lines
5.4 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Kevin Lam <kevin.lam@freescale.com>
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* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <hwconfig.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <fdt_support.h>
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#include <spd_sdram.h>
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#include <vsc7385.h>
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#include <fsl_esdhc.h>
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#if defined(CONFIG_SYS_DRAM_TEST)
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int
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testdram(void)
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{
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uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
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uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
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uint *p;
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printf("Testing DRAM from 0x%08x to 0x%08x\n",
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CONFIG_SYS_MEMTEST_START,
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CONFIG_SYS_MEMTEST_END);
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printf("DRAM test phase 1:\n");
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for (p = pstart; p < pend; p++)
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*p = 0xaaaaaaaa;
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for (p = pstart; p < pend; p++) {
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if (*p != 0xaaaaaaaa) {
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printf("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test phase 2:\n");
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for (p = pstart; p < pend; p++)
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*p = 0x55555555;
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for (p = pstart; p < pend; p++) {
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if (*p != 0x55555555) {
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printf("DRAM test fails at: %08x\n", (uint) p);
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return 1;
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}
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}
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printf("DRAM test passed.\n");
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return 0;
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}
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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phys_size_t initdram(int board_type)
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{
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immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/* Initialize DDR ECC byte */
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus DDR size(bytes) */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
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u32 msize_log2 = __ilog2(msize);
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
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im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
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im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
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udelay(50000);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
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udelay(1000);
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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udelay(1000);
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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sync();
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udelay(1000);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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udelay(2000);
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return CONFIG_SYS_DDR_SIZE;
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}
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#endif /*!CONFIG_SYS_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC837xERDB\n");
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return 0;
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}
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int board_early_init_f(void)
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{
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#ifdef CONFIG_FSL_SERDES
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immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
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u32 spridr = in_be32(&immr->sysconf.spridr);
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/* we check only part num, and don't look for CPU revisions */
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switch (PARTID_NO_E(spridr)) {
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case SPR_8377:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8378:
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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case SPR_8379:
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fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
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FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
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break;
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default:
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printf("serdes not configured: unknown CPU part number: "
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"%04x\n", spridr >> 16);
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break;
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}
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#endif /* CONFIG_FSL_SERDES */
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return 0;
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}
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#ifdef CONFIG_FSL_ESDHC
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int board_mmc_init(bd_t *bd)
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{
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struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
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if (!hwconfig("esdhc"))
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return 0;
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clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
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clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
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return fsl_esdhc_mmc_init(bd);
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}
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#endif
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/*
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* Miscellaneous late-boot configurations
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*
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* If a VSC7385 microcode image is present, then upload it.
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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#ifdef CONFIG_VSC7385_IMAGE
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if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
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CONFIG_VSC7385_IMAGE_SIZE)) {
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puts("Failure uploading VSC7385 microcode.\n");
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rc = 1;
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}
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#endif
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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ft_cpu_setup(blob, bd);
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fdt_fixup_dr_usb(blob, bd);
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fdt_fixup_esdhc(blob, bd);
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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