mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-25 04:19:43 +09:00
329e023868
Set ethernet clock rate to 125 Mhz so that it will work with 1000Mbps, Earlier this is done by FSBL. With this change We can remove the ethernet clock rate code from FSBL. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
90 lines
1.8 KiB
Plaintext
90 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* (C) Copyright 2019 SiFive, Inc
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*/
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/ {
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cpus {
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assigned-clocks = <&prci PRCI_CLK_COREPLL>;
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assigned-clock-rates = <1000000000>;
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u-boot,dm-spl;
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cpu0: cpu@0 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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status = "okay";
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cpu0_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu1: cpu@1 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu1_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu2: cpu@2 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu2_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu3: cpu@3 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu3_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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cpu4: cpu@4 {
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clocks = <&prci PRCI_CLK_COREPLL>;
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u-boot,dm-spl;
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cpu4_intc: interrupt-controller {
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u-boot,dm-spl;
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};
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};
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};
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soc {
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u-boot,dm-spl;
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otp: otp@10070000 {
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compatible = "sifive,fu540-c000-otp";
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reg = <0x0 0x10070000 0x0 0x0FFF>;
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fuse-count = <0x1000>;
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};
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clint@2000000 {
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compatible = "riscv,clint0";
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 &cpu1_intc 3 &cpu1_intc 7 &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>;
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reg = <0x0 0x2000000 0x0 0xc0000>;
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u-boot,dm-spl;
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};
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dmc: dmc@100b0000 {
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compatible = "sifive,fu540-c000-ddr";
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reg = <0x0 0x100b0000 0x0 0x0800
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0x0 0x100b2000 0x0 0x2000
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0x0 0x100b8000 0x0 0x0fff>;
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clocks = <&prci PRCI_CLK_DDRPLL>;
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clock-frequency = <933333324>;
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u-boot,dm-spl;
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};
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};
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};
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&prci {
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u-boot,dm-spl;
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};
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&uart0 {
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u-boot,dm-spl;
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};
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&qspi2 {
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u-boot,dm-spl;
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};
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ð0 {
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assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
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assigned-clock-rates = <125000000>;
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};
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