mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-19 01:27:59 +09:00
e4426d07b6
This patch moves platform specific information for GPMC and ELM controller into separate header files, so that any derivative devices do not mess other header files. Platform specific information added into arch-xx/../hardware.h - CPU related platform specific details like base-address of GPMC and ELM Platform specific information added into arch-xx/../mem.h - Generic configs for GPMC and ELM initialization. - Hardware parameters or constrains specific to GPMC and ELM IP like; number of max number of chip-selects available Signed-off-by: Pekon Gupta <pekon@ti.com>
111 lines
2.7 KiB
C
111 lines
2.7 KiB
C
/*
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* (C) Copyright 2006-2010
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* Texas Instruments, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _CPU_H
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#define _CPU_H
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#endif /* !(__KERNEL_STRICT_NAMES || __ASSEMBLY__) */
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#include <asm/arch/hardware.h>
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct gptimer {
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u32 tidr; /* 0x00 r */
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u8 res[0xc];
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u32 tiocp_cfg; /* 0x10 rw */
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u32 tistat; /* 0x14 r */
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u32 tisr; /* 0x18 rw */
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u32 tier; /* 0x1c rw */
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u32 twer; /* 0x20 rw */
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u32 tclr; /* 0x24 rw */
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u32 tcrr; /* 0x28 rw */
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u32 tldr; /* 0x2c rw */
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u32 ttgr; /* 0x30 rw */
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u32 twpc; /* 0x34 r */
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u32 tmar; /* 0x38 rw */
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u32 tcar1; /* 0x3c r */
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u32 tcicr; /* 0x40 rw */
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u32 tcar2; /* 0x44 r */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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/* enable sys_clk NO-prescale /1 */
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#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
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/* Watchdog */
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#ifndef __KERNEL_STRICT_NAMES
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#ifndef __ASSEMBLY__
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struct watchdog {
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u8 res1[0x34];
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u32 wwps; /* 0x34 r */
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u8 res2[0x10];
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u32 wspr; /* 0x48 rw */
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};
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL_STRICT_NAMES */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* I2C base */
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#define I2C_BASE1 (OMAP44XX_L4_PER_BASE + 0x70000)
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#define I2C_BASE2 (OMAP44XX_L4_PER_BASE + 0x72000)
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#define I2C_BASE3 (OMAP44XX_L4_PER_BASE + 0x60000)
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#define I2C_BASE4 (OMAP44XX_L4_PER_BASE + 0x350000)
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/* MUSB base */
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#define MUSB_BASE (OMAP44XX_L4_CORE_BASE + 0xAB000)
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/* OMAP4 GPIO registers */
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#define OMAP_GPIO_REVISION 0x0000
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#define OMAP_GPIO_SYSCONFIG 0x0010
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#define OMAP_GPIO_SYSSTATUS 0x0114
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#define OMAP_GPIO_IRQSTATUS1 0x0118
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#define OMAP_GPIO_IRQSTATUS2 0x0128
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#define OMAP_GPIO_IRQENABLE2 0x012c
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#define OMAP_GPIO_IRQENABLE1 0x011c
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#define OMAP_GPIO_WAKE_EN 0x0120
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#define OMAP_GPIO_CTRL 0x0130
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#define OMAP_GPIO_OE 0x0134
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#define OMAP_GPIO_DATAIN 0x0138
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#define OMAP_GPIO_DATAOUT 0x013c
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#define OMAP_GPIO_LEVELDETECT0 0x0140
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#define OMAP_GPIO_LEVELDETECT1 0x0144
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#define OMAP_GPIO_RISINGDETECT 0x0148
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#define OMAP_GPIO_FALLINGDETECT 0x014c
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#define OMAP_GPIO_DEBOUNCE_EN 0x0150
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#define OMAP_GPIO_DEBOUNCE_VAL 0x0154
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#define OMAP_GPIO_CLEARIRQENABLE1 0x0160
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#define OMAP_GPIO_SETIRQENABLE1 0x0164
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#define OMAP_GPIO_CLEARWKUENA 0x0180
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#define OMAP_GPIO_SETWKUENA 0x0184
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#define OMAP_GPIO_CLEARDATAOUT 0x0190
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#define OMAP_GPIO_SETDATAOUT 0x0194
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/*
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* PRCM
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*/
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/* PRM */
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#define PRM_BASE 0x4A306000
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#define PRM_DEVICE_BASE (PRM_BASE + 0x1B00)
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#define PRM_RSTCTRL PRM_DEVICE_BASE
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#define PRM_RSTCTRL_RESET 0x01
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#define PRM_RSTST (PRM_DEVICE_BASE + 0x4)
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#define PRM_RSTST_WARM_RESET_MASK 0x07EA
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#endif /* _CPU_H */
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