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https://github.com/brain-hackers/u-boot-brain
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eb53941206
Boot space translation utilizes the pre-translation address to select the DDR controller target. However, the post-translation address will be presented to the selected DDR controller. It is possible that the pre- translation address selects one DDR controller but the post-translation address exists in a different DDR controller when using certain DDR controller interleaving modes. The device may fail to boot under these circumstances. Note that a DDR MSE error will not be detected since DDR controller bounds registers are programmed to be the same when configured for DDR controller interleaving. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com> |
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| .. | ||
| _ashldi3.S | ||
| _ashrdi3.S | ||
| _lshrdi3.S | ||
| bat_rw.c | ||
| board.c | ||
| bootm.c | ||
| cache.c | ||
| extable.c | ||
| ide.c | ||
| ide.h | ||
| interrupts.c | ||
| kgdb.c | ||
| Makefile | ||
| memcpy_mpc5200.c | ||
| ppccache.S | ||
| ppcstring.S | ||
| reloc.S | ||
| ticks.S | ||
| time.c | ||