mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 21:56:21 +09:00
a471db07fb
This patch updates the "normal" Bamboo NOR booting port, so that it is compatible with the coming soon NAND booting Bamboo port. It also enables the 2nd NAND flash on the Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
172 lines
5.0 KiB
C
172 lines
5.0 KiB
C
/*
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* (C) Copyright 2004-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
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* Add support for Am29F016D and dynamic switch setting.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Modified 4/5/2001
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* Wait for completion of each sector erase command issued
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* 4/5/2001
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* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
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*/
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#include <common.h>
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#include <ppc4xx.h>
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#include <asm/processor.h>
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#include <ppc440.h>
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#include "bamboo.h"
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#undef DEBUG
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#ifdef DEBUG
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#define DEBUGF(x...) printf(x)
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#else
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#define DEBUGF(x...)
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#endif /* DEBUG */
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flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
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/*
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* Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
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*/
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static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
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{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
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{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66 */
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{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash */
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{0x87F00000, 0x87F80000, 0xFFC00001}, /* 3:boot from big flash 33*/
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{0x87F00000, 0x87F80000, 0xFFC00001}, /* 4:boot from big flash 66*/
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{0x00000000, 0x00000000, 0x00000000}, /* 5:boot from */
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{0x00000000, 0x00000000, 0x00000000}, /* 6:boot from pci 66 */
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{0x00000000, 0x00000000, 0x00000000}, /* 7:boot from */
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{0x87C00001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
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};
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/*
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* include common flash code (for amcc boards)
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*/
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#include "../common/flash.c"
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/*-----------------------------------------------------------------------
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* Functions
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*/
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static ulong flash_get_size(vu_long * addr, flash_info_t * info);
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static int write_word(flash_info_t * info, ulong dest, ulong data);
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/*-----------------------------------------------------------------------
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*/
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unsigned long flash_init(void)
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{
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unsigned long total_b = 0;
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unsigned long size_b[CFG_MAX_FLASH_BANKS];
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unsigned short index = 0;
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int i;
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unsigned long val;
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unsigned long ebc_boot_size;
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unsigned long boot_selection;
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mfsdr(sdr_pstrp0, val);
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index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29;
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if ((index == 5) || (index == 7)) {
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/*
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* Boot Settings in IIC EEprom address 0xA8 or 0xA4
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* Read Serial Device Strap Register1 in PPC440EP
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*/
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mfsdr(sdr_sdstp1, val);
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boot_selection = val & SDR0_SDSTP1_BOOT_SEL_MASK;
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ebc_boot_size = val & SDR0_SDSTP1_EBC_ROM_BS_MASK;
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switch(boot_selection) {
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case SDR0_SDSTP1_BOOT_SEL_EBC:
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switch(ebc_boot_size) {
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case SDR0_SDSTP1_EBC_ROM_BS_16BIT:
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index = 3;
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break;
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case SDR0_SDSTP1_EBC_ROM_BS_8BIT:
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index = 0;
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break;
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}
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break;
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case SDR0_SDSTP1_BOOT_SEL_PCI:
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index = 1;
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break;
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case SDR0_SDSTP1_BOOT_SEL_NDFC:
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index = 2;
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break;
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}
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} else if (index == 0) {
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if (in8(FPGA_SETTING_REG) & FPGA_SET_REG_OP_CODE_FLASH_ABOVE) {
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index = 8; /* sram below op code flash -> new index 8 */
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}
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}
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DEBUGF("\n");
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DEBUGF("FLASH: Index: %d\n", index);
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/* Init: no FLASHes known */
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for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
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flash_info[i].flash_id = FLASH_UNKNOWN;
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flash_info[i].sector_count = -1;
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flash_info[i].size = 0;
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/* check whether the address is 0 */
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if (flash_addr_table[index][i] == 0)
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continue;
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DEBUGF("Detection bank %d...\n", i);
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/* call flash_get_size() to initialize sector address */
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size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i],
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&flash_info[i]);
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flash_info[i].size = size_b[i];
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if (flash_info[i].flash_id == FLASH_UNKNOWN) {
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printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
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i, size_b[i], size_b[i] << 20);
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flash_info[i].sector_count = -1;
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flash_info[i].size = 0;
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}
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
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CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
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&flash_info[i]);
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#if defined(CFG_ENV_IS_IN_FLASH)
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(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
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CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
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&flash_info[i]);
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#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND)
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(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
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CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
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&flash_info[i]);
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#endif
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#endif
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total_b += flash_info[i].size;
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}
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return total_b;
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}
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