mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 02:48:51 +09:00
![Masahiro Yamada](/assets/img/avatar_default.png)
Starting from PXs3, the bit fields of RSTCTRL, CLKCTRL registers will change every SoC. There is no more point to define bitfields in the common header file. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
38 lines
1.2 KiB
C
38 lines
1.2 KiB
C
/*
|
|
* UniPhier SC (System Control) block registers for ARMv8 SoCs
|
|
*
|
|
* Copyright (C) 2016 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#ifndef SC64_REGS_H
|
|
#define SC64_REGS_H
|
|
|
|
#define SC_BASE_ADDR 0x61840000
|
|
|
|
#define SC_RSTCTRL (SC_BASE_ADDR | 0x2000)
|
|
#define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008)
|
|
#define SC_RSTCTRL4 (SC_BASE_ADDR | 0x200c)
|
|
#define SC_RSTCTRL5 (SC_BASE_ADDR | 0x2010)
|
|
#define SC_RSTCTRL6 (SC_BASE_ADDR | 0x2014)
|
|
#define SC_RSTCTRL7 (SC_BASE_ADDR | 0x2018)
|
|
|
|
#define SC_CLKCTRL (SC_BASE_ADDR | 0x2100)
|
|
#define SC_CLKCTRL3 (SC_BASE_ADDR | 0x2108)
|
|
#define SC_CLKCTRL4 (SC_BASE_ADDR | 0x210c)
|
|
#define SC_CLKCTRL5 (SC_BASE_ADDR | 0x2110)
|
|
#define SC_CLKCTRL6 (SC_BASE_ADDR | 0x2114)
|
|
#define SC_CLKCTRL7 (SC_BASE_ADDR | 0x2118)
|
|
|
|
#define SC_CA72_GEARST (SC_BASE_ADDR | 0x8000)
|
|
#define SC_CA72_GEARSET (SC_BASE_ADDR | 0x8004)
|
|
#define SC_CA72_GEARUPD (SC_BASE_ADDR | 0x8008)
|
|
#define SC_CA53_GEARST (SC_BASE_ADDR | 0x8080)
|
|
#define SC_CA53_GEARSET (SC_BASE_ADDR | 0x8084)
|
|
#define SC_CA53_GEARUPD (SC_BASE_ADDR | 0x8088)
|
|
#define SC_CA_GEARUPD (1 << 0)
|
|
|
|
#endif /* SC64_REGS_H */
|