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https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
158 lines
3.0 KiB
C
158 lines
3.0 KiB
C
/*
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* Copyright (C) 2011-2015 Panasonic Corporation
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include "sg-regs.h"
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#include "init.h"
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static int __uniphier_memconf_init(const struct uniphier_board_data *bd,
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int have_ch2)
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{
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u32 val = 0;
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unsigned long size_per_word;
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/* set up ch0 */
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switch (bd->dram_ch[0].width) {
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case 16:
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val |= SG_MEMCONF_CH0_NUM_1;
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size_per_word = bd->dram_ch[0].size;
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break;
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case 32:
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val |= SG_MEMCONF_CH0_NUM_2;
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size_per_word = bd->dram_ch[0].size >> 1;
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break;
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default:
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pr_err("error: unsupported DRAM ch0 width\n");
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return -EINVAL;
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}
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switch (size_per_word) {
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case SZ_64M:
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val |= SG_MEMCONF_CH0_SZ_64M;
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break;
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case SZ_128M:
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val |= SG_MEMCONF_CH0_SZ_128M;
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break;
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case SZ_256M:
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val |= SG_MEMCONF_CH0_SZ_256M;
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break;
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case SZ_512M:
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val |= SG_MEMCONF_CH0_SZ_512M;
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break;
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case SZ_1G:
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val |= SG_MEMCONF_CH0_SZ_1G;
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break;
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default:
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pr_err("error: unsupported DRAM ch0 size\n");
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return -EINVAL;
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}
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/* set up ch1 */
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switch (bd->dram_ch[1].width) {
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case 16:
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val |= SG_MEMCONF_CH1_NUM_1;
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size_per_word = bd->dram_ch[1].size;
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break;
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case 32:
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val |= SG_MEMCONF_CH1_NUM_2;
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size_per_word = bd->dram_ch[1].size >> 1;
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break;
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default:
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pr_err("error: unsupported DRAM ch1 width\n");
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return -EINVAL;
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}
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switch (size_per_word) {
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case SZ_64M:
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val |= SG_MEMCONF_CH1_SZ_64M;
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break;
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case SZ_128M:
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val |= SG_MEMCONF_CH1_SZ_128M;
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break;
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case SZ_256M:
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val |= SG_MEMCONF_CH1_SZ_256M;
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break;
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case SZ_512M:
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val |= SG_MEMCONF_CH1_SZ_512M;
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break;
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case SZ_1G:
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val |= SG_MEMCONF_CH1_SZ_1G;
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break;
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default:
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pr_err("error: unsupported DRAM ch1 size\n");
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return -EINVAL;
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}
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/* is sparse mem? */
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if (bd->flags & UNIPHIER_BD_DRAM_SPARSE)
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val |= SG_MEMCONF_SPARSEMEM;
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if (!have_ch2)
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goto out;
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if (!bd->dram_ch[2].size) {
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val |= SG_MEMCONF_CH2_DISABLE;
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goto out;
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}
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/* set up ch2 */
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switch (bd->dram_ch[2].width) {
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case 16:
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val |= SG_MEMCONF_CH2_NUM_1;
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size_per_word = bd->dram_ch[2].size;
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break;
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case 32:
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val |= SG_MEMCONF_CH2_NUM_2;
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size_per_word = bd->dram_ch[2].size >> 1;
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break;
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default:
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pr_err("error: unsupported DRAM ch2 width\n");
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return -EINVAL;
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}
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switch (size_per_word) {
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case SZ_64M:
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val |= SG_MEMCONF_CH2_SZ_64M;
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break;
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case SZ_128M:
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val |= SG_MEMCONF_CH2_SZ_128M;
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break;
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case SZ_256M:
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val |= SG_MEMCONF_CH2_SZ_256M;
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break;
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case SZ_512M:
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val |= SG_MEMCONF_CH2_SZ_512M;
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break;
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case SZ_1G:
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val |= SG_MEMCONF_CH2_SZ_1G;
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break;
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default:
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pr_err("error: unsupported DRAM ch2 size\n");
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return -EINVAL;
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}
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out:
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writel(val, SG_MEMCONF);
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return 0;
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}
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int uniphier_memconf_2ch_init(const struct uniphier_board_data *bd)
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{
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return __uniphier_memconf_init(bd, 0);
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}
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int uniphier_memconf_3ch_init(const struct uniphier_board_data *bd)
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{
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return __uniphier_memconf_init(bd, 1);
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}
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