mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-09 20:56:16 +09:00
0b8f6378cb
The Arria10 SPL is a complete mess of calls to functions which are called in the wrong context and it is surprise it works at all. This patch tries to clean that mess up by shuffling the function calls around and moving the calls into the correct context. Due to the delicate nature of the reordering, this is done in one huge patch. The following changes happen in this patch: - Security policy init and NIC301 happens first in board_init_f() - The clock init happens very early in board_init_f() in SPL only - arch_early_init_r() only registers the FPGA, just like on Gen5 - arch_early_init_r() is never called from any _f() function - Dedicated FPGA pins are inited in board_init_f() as on Gen5 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
219 lines
6.6 KiB
C
219 lines
6.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#ifndef CLOCK_MANAGER_ARRIA10
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#define CLOCK_MANAGER_ARRIA10
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#ifndef __ASSEMBLER__
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struct socfpga_clock_manager_main_pll {
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u32 vco0;
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u32 vco1;
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u32 en;
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u32 ens;
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u32 enr;
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u32 bypass;
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u32 bypasss;
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u32 bypassr;
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u32 mpuclk;
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u32 nocclk;
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u32 cntr2clk;
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u32 cntr3clk;
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u32 cntr4clk;
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u32 cntr5clk;
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u32 cntr6clk;
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u32 cntr7clk;
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u32 cntr8clk;
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u32 cntr9clk;
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u32 pad_0x48_0x5b[5];
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u32 cntr15clk;
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u32 outrst;
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u32 outrststat;
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u32 nocdiv;
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u32 pad_0x6c_0x80[5];
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};
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struct socfpga_clock_manager_per_pll {
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u32 vco0;
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u32 vco1;
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u32 en;
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u32 ens;
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u32 enr;
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u32 bypass;
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u32 bypasss;
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u32 bypassr;
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u32 pad_0x20_0x27[2];
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u32 cntr2clk;
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u32 cntr3clk;
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u32 cntr4clk;
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u32 cntr5clk;
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u32 cntr6clk;
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u32 cntr7clk;
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u32 cntr8clk;
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u32 cntr9clk;
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u32 pad_0x48_0x5f[6];
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u32 outrst;
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u32 outrststat;
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u32 emacctl;
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u32 gpiodiv;
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u32 pad_0x70_0x80[4];
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};
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struct socfpga_clock_manager_altera {
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u32 mpuclk;
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u32 nocclk;
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u32 mainmisc0;
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u32 mainmisc1;
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u32 perimisc0;
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u32 perimisc1;
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};
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struct socfpga_clock_manager {
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/* clkmgr */
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u32 ctrl;
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u32 intr;
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u32 intrs;
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u32 intrr;
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u32 intren;
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u32 intrens;
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u32 intrenr;
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u32 stat;
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u32 testioctrl;
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u32 _pad_0x24_0x40[7];
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/* mainpllgrp */
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struct socfpga_clock_manager_main_pll main_pll;
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/* perpllgrp */
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struct socfpga_clock_manager_per_pll per_pll;
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struct socfpga_clock_manager_altera altera;
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};
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#ifdef CONFIG_SPL_BUILD
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int cm_basic_init(const void *blob);
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#endif
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unsigned int cm_get_l4_sp_clk_hz(void);
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unsigned long cm_get_mpu_clk_hz(void);
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unsigned int cm_get_qspi_controller_clk_hz(void);
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#endif /* __ASSEMBLER__ */
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#define CLKMGR_ALTERAGRP_MPU_CLK_OFFSET 0x140
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#define CLKMGR_MAINPLL_NOC_CLK_OFFSET 0x144
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#define LOCKED_MASK (CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK | \
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CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK)
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/* value */
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#define CLKMGR_MAINPLL_BYPASS_RESET 0x0000003f
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#define CLKMGR_PERPLL_BYPASS_RESET 0x000000ff
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#define CLKMGR_MAINPLL_VCO0_RESET 0x00010053
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#define CLKMGR_MAINPLL_VCO1_RESET 0x00010001
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#define CLKMGR_PERPLL_VCO0_RESET 0x00010053
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#define CLKMGR_PERPLL_VCO1_RESET 0x00010001
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#define CLKMGR_MAINPLL_VCO0_PSRC_EOSC 0x0
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#define CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC 0x1
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#define CLKMGR_MAINPLL_VCO0_PSRC_F2S 0x2
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#define CLKMGR_PERPLL_VCO0_PSRC_EOSC 0x0
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#define CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC 0x1
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#define CLKMGR_PERPLL_VCO0_PSRC_F2S 0x2
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#define CLKMGR_PERPLL_VCO0_PSRC_MAIN 0x3
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/* mask */
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#define CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK BIT(6)
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#define CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK BIT(7)
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#define CLKMGR_CLKMGR_STAT_MAINPLLLOCKED_SET_MSK BIT(8)
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#define CLKMGR_CLKMGR_STAT_PERPLLLOCKED_SET_MSK BIT(9)
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#define CLKMGR_CLKMGR_STAT_BOOTCLKSRC_SET_MSK BIT(17)
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#define CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
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#define CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK BIT(1)
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#define CLKMGR_MAINPLL_VCO0_EN_SET_MSK BIT(2)
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#define CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
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#define CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
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#define CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK BIT(0)
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#define CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK BIT(1)
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#define CLKMGR_PERPLL_VCO0_EN_SET_MSK BIT(2)
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#define CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK BIT(3)
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#define CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK BIT(4)
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#define CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK BIT(0)
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#define CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK BIT(1)
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#define CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK BIT(2)
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#define CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK BIT(3)
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#define CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK BIT(8)
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#define CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK BIT(9)
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#define CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK BIT(10)
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#define CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK BIT(11)
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#define CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK BIT(0)
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#define CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK 0x00000300
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#define CLKMGR_PERPLL_EN_RESET 0x00000f7f
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#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK BIT(5)
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#define CLKMGR_MAINPLL_VCO0_PSRC_MSK 0x00000003
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#define CLKMGR_MAINPLL_VCO1_NUMER_MSK 0x00001fff
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#define CLKMGR_MAINPLL_VCO1_DENOM_MSK 0x0000003f
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#define CLKMGR_MAINPLL_CNTRCLK_MSK 0x000003ff
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#define CLKMGR_PERPLL_VCO0_PSRC_MSK 0x00000003
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#define CLKMGR_PERPLL_VCO1_NUMER_MSK 0x00001fff
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#define CLKMGR_PERPLL_VCO1_DENOM_MSK 0x0000003f
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#define CLKMGR_PERPLL_CNTRCLK_MSK 0x000003ff
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#define CLKMGR_MAINPLL_MPUCLK_SRC_MSK 0x00000007
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#define CLKMGR_MAINPLL_MPUCLK_CNT_MSK 0x000003ff
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#define CLKMGR_MAINPLL_MPUCLK_SRC_MAIN 0
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#define CLKMGR_MAINPLL_MPUCLK_SRC_PERI 1
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#define CLKMGR_MAINPLL_MPUCLK_SRC_OSC1 2
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#define CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC 3
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#define CLKMGR_MAINPLL_MPUCLK_SRC_FPGA 4
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#define CLKMGR_MAINPLL_NOCDIV_MSK 0x00000003
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#define CLKMGR_MAINPLL_NOCCLK_CNT_MSK 0x000003ff
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#define CLKMGR_MAINPLL_NOCCLK_SRC_MSK 0x00000007
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#define CLKMGR_MAINPLL_NOCCLK_SRC_MAIN 0
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#define CLKMGR_MAINPLL_NOCCLK_SRC_PERI 1
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#define CLKMGR_MAINPLL_NOCCLK_SRC_OSC1 2
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#define CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC 3
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#define CLKMGR_MAINPLL_NOCCLK_SRC_FPGA 4
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#define CLKMGR_PERPLLGRP_SRC_MSK 0x00000007
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#define CLKMGR_PERPLLGRP_SRC_MAIN 0
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#define CLKMGR_PERPLLGRP_SRC_PERI 1
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#define CLKMGR_PERPLLGRP_SRC_OSC1 2
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#define CLKMGR_PERPLLGRP_SRC_INTOSC 3
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#define CLKMGR_PERPLLGRP_SRC_FPGA 4
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/* bit shifting macro */
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#define CLKMGR_MAINPLL_VCO0_PSRC_LSB 8
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#define CLKMGR_PERPLL_VCO0_PSRC_LSB 8
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#define CLKMGR_MAINPLL_VCO1_DENOM_LSB 16
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#define CLKMGR_PERPLL_VCO1_DENOM_LSB 16
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#define CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB 16
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#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
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#define CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB 0
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#define CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB 8
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#define CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB 16
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#define CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB 24
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#define CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB 26
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#define CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB 28
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#define CLKMGR_MAINPLL_MPUCLK_SRC_LSB 16
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#define CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB 16
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#define CLKMGR_MAINPLL_NOCCLK_SRC_LSB 16
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#define CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB 16
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#define CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_CNTR2CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_CNTR3CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_CNTR4CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_CNTR5CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_CNTR6CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_CNTR8CLK_SRC_LSB 16
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#define CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB 26
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#define CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB 27
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#define CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB 28
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/* PLL ramping work around */
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#define CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ 900000000
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#define CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ 300000000
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#define CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ 100000000
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#define CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ 33000000
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#define CLKMGR_STAT_BUSY BIT(0)
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#endif /* CLOCK_MANAGER_ARRIA10 */
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