mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 03:06:16 +09:00
0b8f6378cb
The Arria10 SPL is a complete mess of calls to functions which are called in the wrong context and it is surprise it works at all. This patch tries to clean that mess up by shuffling the function calls around and moving the calls into the correct context. Due to the delicate nature of the reordering, this is done in one huge patch. The following changes happen in this patch: - Security policy init and NIC301 happens first in board_init_f() - The clock init happens very early in board_init_f() in SPL only - arch_early_init_r() only registers the FPGA, just like on Gen5 - arch_early_init_r() is never called from any _f() function - Dedicated FPGA pins are inited in board_init_f() as on Gen5 Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
89 lines
1.8 KiB
C
89 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Altera SoCFPGA common board code
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*
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* Copyright (C) 2015 Marek Vasut <marex@denx.de>
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*/
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/clock_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/io.h>
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#include <usb.h>
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#include <usb/dwc2_udc.h>
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DECLARE_GLOBAL_DATA_PTR;
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void s_init(void) {
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#ifndef CONFIG_ARM64
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/*
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* Preconfigure ACTLR and CPACR, make sure Write Full Line of Zeroes
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* is disabled in ACTLR.
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* This is optional on CycloneV / ArriaV.
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* This is mandatory on Arria10, otherwise Linux refuses to boot.
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*/
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asm volatile(
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"mcr p15, 0, %0, c1, c0, 1\n"
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"mcr p15, 0, %0, c1, c0, 2\n"
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"isb\n"
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"dsb\n"
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::"r"(0x0));
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#endif
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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/* Address of boot parameters for ATAG (if ATAG is used) */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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#ifdef CONFIG_USB_GADGET
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struct dwc2_plat_otg_data socfpga_otg_data = {
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.usb_gusbcfg = 0x1417,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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int node[2], count;
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fdt_addr_t addr;
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count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
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COMPAT_ALTERA_SOCFPGA_DWC2USB,
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node, 2);
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if (count <= 0) /* No controller found. */
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return 0;
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addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
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if (addr == FDT_ADDR_T_NONE) {
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printf("UDC Controller has no 'reg' property!\n");
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return -EINVAL;
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}
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/* Patch the address from OF into the controller pdata. */
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socfpga_otg_data.regs_otg = addr;
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return dwc2_udc_probe(&socfpga_otg_data);
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}
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int g_dnl_board_usb_cable_connected(void)
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{
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return 1;
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}
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#endif
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