mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-24 02:48:51 +09:00
![Tien Fong Chee](/assets/img/avatar_default.png)
This DT binding doc is porting from Linux DT binding doc. commit 1adcbea4201a6852362aa5ece573f1f169b28113 Add a device tree bindings document for the SoCFPGA Arria10 FPGA Manager driver. Signed-off-by: Alan Tull <atull@opensource.altera.com> Acked-by: Rob Herring <robh@kernel.org> Acked-By: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
20 lines
629 B
Plaintext
20 lines
629 B
Plaintext
Altera SOCFPGA Arria10 FPGA Manager
|
|
|
|
Required properties:
|
|
- compatible : should contain "altr,socfpga-a10-fpga-mgr"
|
|
- reg : base address and size for memory mapped io.
|
|
- The first index is for FPGA manager register access.
|
|
- The second index is for writing FPGA configuration data.
|
|
- resets : Phandle and reset specifier for the device's reset.
|
|
- clocks : Clocks used by the device.
|
|
|
|
Example:
|
|
|
|
fpga_mgr: fpga-mgr@ffd03000 {
|
|
compatible = "altr,socfpga-a10-fpga-mgr";
|
|
reg = <0xffd03000 0x100
|
|
0xffcfe400 0x20>;
|
|
clocks = <&l4_mp_clk>;
|
|
resets = <&rst FPGAMGR_RESET>;
|
|
};
|