mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
0f89c54be9
The individual i2c commands imd, imm, inm, imw, icrc32, iprobe, iloop, and isdram are no longer available so all references to them have been updated to the new form of "i2c <cmd>". Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
291 lines
8.0 KiB
C
291 lines
8.0 KiB
C
/*
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* (C) Copyright 2004 Tundra Semiconductor Corp.
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* Author: Alex Bounine
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <config.h>
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#include <common.h>
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#include <tsi108.h>
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#if defined(CONFIG_CMD_I2C)
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#define I2C_DELAY 100000
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#undef DEBUG_I2C
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#ifdef DEBUG_I2C
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#define DPRINT(x) printf (x)
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#else
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#define DPRINT(x)
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#endif
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/* All functions assume that Tsi108 I2C block is the only master on the bus */
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/* I2C read helper function */
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void i2c_init(int speed, int slaveaddr)
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{
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/*
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* The TSI108 has a fixed I2C clock rate and doesn't support slave
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* operation. This function only exists as a stub to fit into the
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* U-Boot I2C API.
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*/
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}
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static int i2c_read_byte (
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uint i2c_chan, /* I2C channel number: 0 - main, 1 - SDC SPD */
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uchar chip_addr,/* I2C device address on the bus */
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uint byte_addr, /* Byte address within I2C device */
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uchar * buffer /* pointer to data buffer */
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)
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{
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u32 temp;
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u32 to_count = I2C_DELAY;
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u32 op_status = TSI108_I2C_TIMEOUT_ERR;
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u32 chan_offset = TSI108_I2C_OFFSET;
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DPRINT (("I2C read_byte() %d 0x%02x 0x%02x\n",
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i2c_chan, chip_addr, byte_addr));
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if (0 != i2c_chan)
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chan_offset = TSI108_I2C_SDRAM_OFFSET;
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/* Check if I2C operation is in progress */
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
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if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS |
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I2C_CNTRL2_START))) {
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/* Set device address and operation (read = 0) */
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temp = (byte_addr << 16) | ((chip_addr & 0x07) << 8) |
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((chip_addr >> 3) & 0x0F);
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL1) =
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temp;
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/* Issue the read command
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* (at this moment all other parameters are 0
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* (size = 1 byte, lane = 0)
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*/
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2) =
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(I2C_CNTRL2_START);
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/* Wait until operation completed */
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do {
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/* Read I2C operation status */
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + chan_offset + I2C_CNTRL2);
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if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_START))) {
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if (0 == (temp &
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(I2C_CNTRL2_I2C_CFGERR |
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I2C_CNTRL2_I2C_TO_ERR))
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) {
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op_status = TSI108_I2C_SUCCESS;
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE +
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chan_offset +
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I2C_RD_DATA);
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*buffer = (u8) (temp & 0xFF);
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} else {
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/* report HW error */
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op_status = TSI108_I2C_IF_ERROR;
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DPRINT (("I2C HW error reported: 0x%02x\n", temp));
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}
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break;
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}
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} while (to_count--);
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} else {
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op_status = TSI108_I2C_IF_BUSY;
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DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
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}
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DPRINT (("I2C read_byte() status: 0x%02x\n", op_status));
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return op_status;
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}
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/*
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* I2C Read interface as defined in "include/i2c.h" :
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* chip_addr: I2C chip address, range 0..127
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* (to read from SPD channel EEPROM use (0xD0 ... 0xD7)
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* NOTE: The bit 7 in the chip_addr serves as a channel select.
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* This hack is for enabling "i2c sdram" command on Tsi108 boards
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* without changes to common code. Used for I2C reads only.
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* byte_addr: Memory or register address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one
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* register)
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* buffer: Pointer to destination buffer for data to be read
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* len: How many bytes to read
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int i2c_read (uchar chip_addr, uint byte_addr, int alen,
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uchar * buffer, int len)
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{
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u32 op_status = TSI108_I2C_PARAM_ERR;
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u32 i2c_if = 0;
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/* Hack to support second (SPD) I2C controller (SPD EEPROM read only).*/
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if (0xD0 == (chip_addr & ~0x07)) {
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i2c_if = 1;
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chip_addr &= 0x7F;
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}
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/* Check for valid I2C address */
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if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
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while (len--) {
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op_status = i2c_read_byte(i2c_if, chip_addr, byte_addr++, buffer++);
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if (TSI108_I2C_SUCCESS != op_status) {
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DPRINT (("I2C read_byte() failed: 0x%02x (%d left)\n", op_status, len));
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break;
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}
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}
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}
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DPRINT (("I2C read() status: 0x%02x\n", op_status));
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return op_status;
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}
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/* I2C write helper function */
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static int i2c_write_byte (uchar chip_addr,/* I2C device address on the bus */
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uint byte_addr, /* Byte address within I2C device */
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uchar * buffer /* pointer to data buffer */
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)
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{
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u32 temp;
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u32 to_count = I2C_DELAY;
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u32 op_status = TSI108_I2C_TIMEOUT_ERR;
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/* Check if I2C operation is in progress */
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
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if (0 == (temp & (I2C_CNTRL2_RD_STATUS | I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
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/* Place data into the I2C Tx Register */
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
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I2C_TX_DATA) = (u32) * buffer;
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/* Set device address and operation */
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temp =
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I2C_CNTRL1_I2CWRITE | (byte_addr << 16) |
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((chip_addr & 0x07) << 8) | ((chip_addr >> 3) & 0x0F);
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
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I2C_CNTRL1) = temp;
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/* Issue the write command (at this moment all other parameters
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* are 0 (size = 1 byte, lane = 0)
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*/
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*(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET +
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I2C_CNTRL2) = (I2C_CNTRL2_START);
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op_status = TSI108_I2C_TIMEOUT_ERR;
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/* Wait until operation completed */
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do {
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/* Read I2C operation status */
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temp = *(u32 *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_I2C_OFFSET + I2C_CNTRL2);
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if (0 == (temp & (I2C_CNTRL2_WR_STATUS | I2C_CNTRL2_START))) {
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if (0 == (temp &
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(I2C_CNTRL2_I2C_CFGERR |
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I2C_CNTRL2_I2C_TO_ERR))) {
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op_status = TSI108_I2C_SUCCESS;
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} else {
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/* report detected HW error */
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op_status = TSI108_I2C_IF_ERROR;
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DPRINT (("I2C HW error reported: 0x%02x\n", temp));
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}
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break;
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}
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} while (to_count--);
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} else {
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op_status = TSI108_I2C_IF_BUSY;
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DPRINT (("I2C Transaction start failed: 0x%02x\n", temp));
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}
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return op_status;
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}
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/*
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* I2C Write interface as defined in "include/i2c.h" :
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* chip_addr: I2C chip address, range 0..127
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* byte_addr: Memory or register address within the chip
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* alen: Number of bytes to use for addr (typically 1, 2 for larger
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* memories, 0 for register type devices with only one
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* register)
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* buffer: Pointer to data to be written
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* len: How many bytes to write
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int i2c_write (uchar chip_addr, uint byte_addr, int alen, uchar * buffer,
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int len)
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{
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u32 op_status = TSI108_I2C_PARAM_ERR;
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/* Check for valid I2C address */
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if (chip_addr <= 0x7F && (byte_addr + len) <= (0x01 << (alen * 8))) {
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while (len--) {
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op_status =
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i2c_write_byte (chip_addr, byte_addr++, buffer++);
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if (TSI108_I2C_SUCCESS != op_status) {
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DPRINT (("I2C write_byte() failed: 0x%02x (%d left)\n", op_status, len));
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break;
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}
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}
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}
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return op_status;
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}
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/*
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* I2C interface function as defined in "include/i2c.h".
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* Probe the given I2C chip address by reading single byte from offset 0.
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* Returns 0 if a chip responded, not 0 on failure.
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*/
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int i2c_probe (uchar chip)
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{
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u32 tmp;
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/*
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* Try to read the first location of the chip.
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* The Tsi108 HW doesn't support sending just the chip address
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* and checkong for an <ACK> back.
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*/
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return i2c_read (chip, 0, 1, (uchar *)&tmp, 1);
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}
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#endif
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