mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-23 10:28:51 +09:00
![Philipp Tomsich](/assets/img/avatar_default.png)
On the RK3399, we will have either OF_PLATDATA or full OF_CONTROL enabled: this allows the use of syscon to retrieve the addresses of GRF and SGRF (except for the early debug UART setup, which runs so early that the device-model is not initialised). This removes the hard-coded addresses and goes through syscon to retrieve the base-addresses of GRF and SGRF. After that, we use the structure definitions to locate the respective registers. In addition to this, the inclusion of header files is also cleaned up: - all headers are included at the beginning (there was a spurious inclusion of the grf header from within a function) - all #include statements for unused headers are removed - the remaining #include statements are sorted (while keeping common.h included in front) Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
180 lines
4.1 KiB
C
180 lines
4.1 KiB
C
/*
|
|
* (C) Copyright 2016 Rockchip Electronics Co., Ltd
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/grf_rk3399.h>
|
|
#include <asm/arch/hardware.h>
|
|
#include <asm/arch/periph.h>
|
|
#include <asm/io.h>
|
|
#include <debug_uart.h>
|
|
#include <dm.h>
|
|
#include <dm/pinctrl.h>
|
|
#include <ram.h>
|
|
#include <spl.h>
|
|
#include <syscon.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
u32 spl_boot_device(void)
|
|
{
|
|
return BOOT_DEVICE_MMC1;
|
|
}
|
|
|
|
u32 spl_boot_mode(const u32 boot_device)
|
|
{
|
|
return MMCSD_MODE_RAW;
|
|
}
|
|
|
|
#define TIMER_CHN10_BASE 0xff8680a0
|
|
#define TIMER_END_COUNT_L 0x00
|
|
#define TIMER_END_COUNT_H 0x04
|
|
#define TIMER_INIT_COUNT_L 0x10
|
|
#define TIMER_INIT_COUNT_H 0x14
|
|
#define TIMER_CONTROL_REG 0x1c
|
|
|
|
#define TIMER_EN 0x1
|
|
#define TIMER_FMODE (0 << 1)
|
|
#define TIMER_RMODE (1 << 1)
|
|
|
|
void secure_timer_init(void)
|
|
{
|
|
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_L);
|
|
writel(0xffffffff, TIMER_CHN10_BASE + TIMER_END_COUNT_H);
|
|
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_L);
|
|
writel(0, TIMER_CHN10_BASE + TIMER_INIT_COUNT_H);
|
|
writel(TIMER_EN | TIMER_FMODE, TIMER_CHN10_BASE + TIMER_CONTROL_REG);
|
|
}
|
|
|
|
void board_debug_uart_init(void)
|
|
{
|
|
#define GRF_BASE 0xff770000
|
|
struct rk3399_grf_regs * const grf = (void *)GRF_BASE;
|
|
|
|
#if defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff180000)
|
|
/* Enable early UART0 on the RK3399 */
|
|
rk_clrsetreg(&grf->gpio2c_iomux,
|
|
GRF_GPIO2C0_SEL_MASK,
|
|
GRF_UART0BT_SIN << GRF_GPIO2C0_SEL_SHIFT);
|
|
rk_clrsetreg(&grf->gpio2c_iomux,
|
|
GRF_GPIO2C1_SEL_MASK,
|
|
GRF_UART0BT_SOUT << GRF_GPIO2C1_SEL_SHIFT);
|
|
#else
|
|
/* Enable early UART2 channel C on the RK3399 */
|
|
rk_clrsetreg(&grf->gpio4c_iomux,
|
|
GRF_GPIO4C3_SEL_MASK,
|
|
GRF_UART2DGBC_SIN << GRF_GPIO4C3_SEL_SHIFT);
|
|
rk_clrsetreg(&grf->gpio4c_iomux,
|
|
GRF_GPIO4C4_SEL_MASK,
|
|
GRF_UART2DBGC_SOUT << GRF_GPIO4C4_SEL_SHIFT);
|
|
/* Set channel C as UART2 input */
|
|
rk_clrsetreg(&grf->soc_con7,
|
|
GRF_UART_DBG_SEL_MASK,
|
|
GRF_UART_DBG_SEL_C << GRF_UART_DBG_SEL_SHIFT);
|
|
#endif
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
struct udevice *pinctrl;
|
|
struct udevice *dev;
|
|
struct rk3399_pmusgrf_regs *sgrf;
|
|
struct rk3399_grf_regs *grf;
|
|
int ret;
|
|
|
|
#define EARLY_UART
|
|
#ifdef EARLY_UART
|
|
/*
|
|
* Debug UART can be used from here if required:
|
|
*
|
|
* debug_uart_init();
|
|
* printch('a');
|
|
* printhex8(0x1234);
|
|
* printascii("string");
|
|
*/
|
|
debug_uart_init();
|
|
printascii("U-Boot SPL board init");
|
|
#endif
|
|
|
|
ret = spl_early_init();
|
|
if (ret) {
|
|
debug("spl_early_init() failed: %d\n", ret);
|
|
hang();
|
|
}
|
|
|
|
/*
|
|
* Disable DDR and SRAM security regions.
|
|
*
|
|
* As we are entered from the BootROM, the region from
|
|
* 0x0 through 0xfffff (i.e. the first MB of memory) will
|
|
* be protected. This will cause issues with the DW_MMC
|
|
* driver, which tries to DMA from/to the stack (likely)
|
|
* located in this range.
|
|
*/
|
|
sgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
|
|
rk_clrsetreg(&sgrf->ddr_rgn_con[16], 0x1ff, 0);
|
|
rk_clrreg(&sgrf->slv_secure_con4, 0x2000);
|
|
|
|
/* eMMC clock generator: disable the clock multipilier */
|
|
grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
|
|
rk_clrreg(&grf->emmccore_con[11], 0x0ff);
|
|
|
|
secure_timer_init();
|
|
|
|
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
|
|
if (ret) {
|
|
debug("Pinctrl init failed: %d\n", ret);
|
|
return;
|
|
}
|
|
|
|
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
|
if (ret) {
|
|
debug("DRAM init failed: %d\n", ret);
|
|
return;
|
|
}
|
|
}
|
|
|
|
void spl_board_init(void)
|
|
{
|
|
struct udevice *pinctrl;
|
|
int ret;
|
|
|
|
ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
|
|
if (ret) {
|
|
debug("%s: Cannot find pinctrl device\n", __func__);
|
|
goto err;
|
|
}
|
|
|
|
/* Enable debug UART */
|
|
ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
|
|
if (ret) {
|
|
debug("%s: Failed to set up console UART\n", __func__);
|
|
goto err;
|
|
}
|
|
|
|
preloader_console_init();
|
|
#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
|
|
back_to_bootrom();
|
|
#endif
|
|
|
|
return;
|
|
err:
|
|
printf("spl_board_init: Error %d\n", ret);
|
|
|
|
/* No way to report error here */
|
|
hang();
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
/* Just empty function now - can't decide what to choose */
|
|
debug("%s: %s\n", __func__, name);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|