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![Philipp Tomsich](/assets/img/avatar_default.png)
The back-to-bootrom option is rather unfortunately named CONFIG_ROCKCHIP_SPL_BACK_TO_BOOTROM instead of CONFIG_SPL_ROCKCHIP_BACK_TO_BOOTROM To make is selectable through CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BOOTROM), we need to rename it. At the same time, we introduce a TPL_ variant of the option to give us finer-grained control over when it should be used. This change is motivated by our RK3368 boot process, which returns to the boot ROM only from the TPL stage, but not from the SPL stage. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> [added fix-up for evb-rk3229_defconfig and phycore-rk3288_defconfig:] [fixed inverted CONFIG_IS_ENABLED test for rk3288:] Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> include/configs/rock.h: undef
329 lines
6.7 KiB
C
329 lines
6.7 KiB
C
/*
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* (C) Copyright 2015 Google, Inc
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <i2c.h>
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#include <led.h>
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#include <malloc.h>
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#include <ram.h>
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#include <spl.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/bootrom.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/periph.h>
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#include <asm/arch/sdram.h>
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#include <asm/arch/timer.h>
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#include <dm/pinctrl.h>
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#include <dm/root.h>
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#include <dm/test.h>
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#include <dm/util.h>
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#include <power/regulator.h>
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#include <power/rk8xx_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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u32 spl_boot_device(void)
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{
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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const void *blob = gd->fdt_blob;
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struct udevice *dev;
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const char *bootdev;
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int node;
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int ret;
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bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
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debug("Boot device %s\n", bootdev);
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if (!bootdev)
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goto fallback;
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node = fdt_path_offset(blob, bootdev);
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if (node < 0) {
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debug("node=%d\n", node);
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goto fallback;
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}
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ret = device_get_global_by_of_offset(node, &dev);
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if (ret) {
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debug("device at node %s/%d not found: %d\n", bootdev, node,
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ret);
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goto fallback;
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}
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debug("Found device %s\n", dev->name);
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switch (device_get_uclass_id(dev)) {
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case UCLASS_SPI_FLASH:
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return BOOT_DEVICE_SPI;
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case UCLASS_MMC:
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return BOOT_DEVICE_MMC1;
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default:
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debug("Booting from device uclass '%s' not supported\n",
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dev_get_uclass_name(dev));
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}
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fallback:
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#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
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defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
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defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
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return BOOT_DEVICE_SPI;
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#endif
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return BOOT_DEVICE_MMC1;
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}
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u32 spl_boot_mode(const u32 boot_device)
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{
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return MMCSD_MODE_RAW;
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}
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/* read L2 control register (L2CTLR) */
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static inline uint32_t read_l2ctlr(void)
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{
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uint32_t val = 0;
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asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
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return val;
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}
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/* write L2 control register (L2CTLR) */
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static inline void write_l2ctlr(uint32_t val)
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{
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/*
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* Note: L2CTLR can only be written when the L2 memory system
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* is idle, ie before the MMU is enabled.
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*/
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asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory");
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isb();
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}
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static void configure_l2ctlr(void)
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{
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uint32_t l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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static int configure_emmc(struct udevice *pinctrl)
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{
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#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
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struct gpio_desc desc;
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int ret;
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pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
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/*
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* TODO(sjg@chromium.org): Pick this up from device tree or perhaps
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* use the EMMC_PWREN setting.
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*/
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ret = dm_gpio_lookup_name("D9", &desc);
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if (ret) {
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debug("gpio ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_request(&desc, "emmc_pwren");
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if (ret) {
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debug("gpio_request ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
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if (ret) {
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debug("gpio dir ret=%d\n", ret);
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return ret;
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}
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ret = dm_gpio_set_value(&desc, 1);
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if (ret) {
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debug("gpio value ret=%d\n", ret);
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return ret;
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}
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#endif
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return 0;
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}
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#endif
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#if !defined(CONFIG_SPL_OF_PLATDATA)
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static int phycore_init(void)
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{
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struct udevice *pmic;
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int ret;
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ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
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if (ret)
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return ret;
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#if defined(CONFIG_SPL_POWER_SUPPORT)
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/* Increase USB input current to 2A */
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ret = rk818_spl_configure_usb_input_current(pmic, 2000);
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if (ret)
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return ret;
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/* Close charger when USB lower then 3.26V */
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ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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#endif
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void board_init_f(ulong dummy)
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{
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struct udevice *pinctrl;
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struct udevice *dev;
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int ret;
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/* Example code showing how to enable the debug UART on RK3288 */
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#include <asm/arch/grf_rk3288.h>
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/* Enable early UART on the RK3288 */
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#define GRF_BASE 0xff770000
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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/*
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* Debug UART can be used from here if required:
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*
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* debug_uart_init();
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* printch('a');
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* printhex8(0x1234);
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* printascii("string");
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*/
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debug_uart_init();
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debug("\nspl:debug uart enabled in %s\n", __func__);
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ret = spl_early_init();
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if (ret) {
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debug("spl_early_init() failed: %d\n", ret);
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hang();
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}
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rockchip_timer_init();
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configure_l2ctlr();
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ret = rockchip_get_clk(&dev);
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if (ret) {
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debug("CLK init failed: %d\n", ret);
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return;
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}
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("Pinctrl init failed: %d\n", ret);
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return;
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}
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#if !defined(CONFIG_SPL_OF_PLATDATA)
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if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
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ret = phycore_init();
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if (ret) {
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debug("Failed to set up phycore power settings: %d\n",
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ret);
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return;
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}
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}
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#endif
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debug("\nspl:init dram\n");
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ret = uclass_get_device(UCLASS_RAM, 0, &dev);
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if (ret) {
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debug("DRAM init failed: %d\n", ret);
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return;
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}
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#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
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back_to_bootrom();
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#endif
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}
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static int setup_led(void)
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{
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#ifdef CONFIG_SPL_LED
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struct udevice *dev;
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
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if (!led_name)
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return 0;
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ret = led_get_by_label(led_name, &dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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ret = led_set_on(dev, 1);
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if (ret)
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return ret;
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#endif
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return 0;
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}
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void spl_board_init(void)
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{
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struct udevice *pinctrl;
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int ret;
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ret = setup_led();
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if (ret) {
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debug("LED ret=%d\n", ret);
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hang();
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}
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ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
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if (ret) {
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debug("%s: Cannot find pinctrl device\n", __func__);
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goto err;
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}
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#ifdef CONFIG_SPL_MMC_SUPPORT
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
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if (ret) {
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debug("%s: Failed to set up SD card\n", __func__);
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goto err;
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}
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ret = configure_emmc(pinctrl);
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if (ret) {
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debug("%s: Failed to set up eMMC\n", __func__);
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goto err;
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}
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#endif
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/* Enable debug UART */
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ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
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if (ret) {
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debug("%s: Failed to set up console UART\n", __func__);
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goto err;
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}
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preloader_console_init();
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#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
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back_to_bootrom();
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#endif
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return;
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err:
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printf("spl_board_init: Error %d\n", ret);
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/* No way to report error here */
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hang();
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}
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