mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
89083346d0
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
480 lines
13 KiB
C
480 lines
13 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* Configuration support for Xilinx Spartan3 devices. Based
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* on spartan2.c (Rich Ireland, rireland@enterasys.com).
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*/
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#include <common.h> /* core U-Boot definitions */
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#include <spartan3.h> /* Spartan-II device family */
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/* Define FPGA_DEBUG to get debug printf's */
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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#undef CONFIG_SYS_FPGA_CHECK_BUSY
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#undef CONFIG_SYS_FPGA_PROG_FEEDBACK
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/* Note: The assumption is that we cannot possibly run fast enough to
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* overrun the device (the Slave Parallel mode can free run at 50MHz).
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* If there is a need to operate slower, define CONFIG_FPGA_DELAY in
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* the board config file to slow things down.
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*/
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#ifndef CONFIG_FPGA_DELAY
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#define CONFIG_FPGA_DELAY()
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#endif
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#ifndef CONFIG_SYS_FPGA_WAIT
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#define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
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#endif
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static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize );
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static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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/* static int Spartan3_sp_info( Xilinx_desc *desc ); */
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static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize );
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static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize );
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/* static int Spartan3_ss_info( Xilinx_desc *desc ); */
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/* ------------------------------------------------------------------------- */
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/* Spartan-II Generic Implementation */
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int Spartan3_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Load\n", __FUNCTION__);
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ret_val = Spartan3_ss_load (desc, buf, bsize);
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break;
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Load\n", __FUNCTION__);
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ret_val = Spartan3_sp_load (desc, buf, bsize);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int Spartan3_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL;
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switch (desc->iface) {
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case slave_serial:
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PRINTF ("%s: Launching Slave Serial Dump\n", __FUNCTION__);
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ret_val = Spartan3_ss_dump (desc, buf, bsize);
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break;
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case slave_parallel:
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PRINTF ("%s: Launching Slave Parallel Dump\n", __FUNCTION__);
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ret_val = Spartan3_sp_dump (desc, buf, bsize);
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break;
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default:
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printf ("%s: Unsupported interface type, %d\n",
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__FUNCTION__, desc->iface);
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}
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return ret_val;
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}
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int Spartan3_info( Xilinx_desc *desc )
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{
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return FPGA_SUCCESS;
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}
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/* ------------------------------------------------------------------------- */
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/* Spartan-II Slave Parallel Generic Implementation */
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static int Spartan3_sp_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"pre: 0x%p\n"
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"pgm:\t0x%p\n"
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"init:\t0x%p\n"
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"err:\t0x%p\n"
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"clk:\t0x%p\n"
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"cs:\t0x%p\n"
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"wr:\t0x%p\n"
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"read data:\t0x%p\n"
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"write data:\t0x%p\n"
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"busy:\t0x%p\n"
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"abort:\t0x%p\n",
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"post:\t0x%p\n\n",
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__FUNCTION__, &fn, fn, fn->pre, fn->pgm, fn->init, fn->err,
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fn->clk, fn->cs, fn->wr, fn->rdata, fn->wdata, fn->busy,
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fn->abort, fn->post);
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/*
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* This code is designed to emulate the "Express Style"
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* Continuous Data Loading in Slave Parallel Mode for
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* the Spartan-II Family.
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*/
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf ("Loading FPGA Device %d...\n", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/* Establish the initial state */
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(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
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ts = get_timer (0); /* get current time */
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/* Now wait for INIT and BUSY to go high */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for INIT to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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return FPGA_FAIL;
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}
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} while ((*fn->init) (cookie) && (*fn->busy) (cookie));
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(*fn->wr) (TRUE, TRUE, cookie); /* Assert write, commit */
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(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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/* Load the data */
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while (bytecount < bsize) {
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/* XXX - do we check for an Ctrl-C press in here ??? */
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/* XXX - Check the error bit? */
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(*fn->wdata) (data[bytecount++], TRUE, cookie); /* write the data */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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#ifdef CONFIG_SYS_FPGA_CHECK_BUSY
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ts = get_timer (0); /* get current time */
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while ((*fn->busy) (cookie)) {
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/* XXX - we should have a check in here somewhere to
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* make sure we aren't busy forever... */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for BUSY to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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return FPGA_FAIL;
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}
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}
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#endif
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.'); /* let them know we are alive */
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#endif
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}
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CONFIG_FPGA_DELAY ();
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(*fn->cs) (FALSE, TRUE, cookie); /* Deassert the chip select */
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(*fn->wr) (FALSE, TRUE, cookie); /* Deassert the write pin */
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc ('\n'); /* terminate the dotted line */
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#endif
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/* now check for done signal */
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ts = get_timer (0); /* get current time */
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ret_val = FPGA_SUCCESS;
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while ((*fn->done) (cookie) == FPGA_FAIL) {
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/* XXX - we should have a check in here somewhere to
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* make sure we aren't busy forever... */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for DONE to clear.\n");
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(*fn->abort) (cookie); /* abort the burn */
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ret_val = FPGA_FAIL;
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break;
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}
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}
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/*
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* Run the post configuration function if there is one.
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*/
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if (*fn->post)
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(*fn->post) (cookie);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (ret_val == FPGA_SUCCESS)
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puts ("Done.\n");
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else
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puts ("Fail.\n");
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#endif
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Parallel_fns *fn = desc->iface_fns;
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if (fn) {
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unsigned char *data = (unsigned char *) buf;
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size_t bytecount = 0;
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int cookie = desc->cookie; /* make a local copy */
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printf ("Starting Dump of FPGA Device %d...\n", cookie);
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(*fn->cs) (TRUE, TRUE, cookie); /* Assert chip select, commit */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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/* dump the data */
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while (bytecount < bsize) {
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/* XXX - do we check for an Ctrl-C press in here ??? */
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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(*fn->rdata) (&(data[bytecount++]), cookie); /* read the data */
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.'); /* let them know we are alive */
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#endif
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}
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(*fn->cs) (FALSE, FALSE, cookie); /* Deassert the chip select */
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc ('\n'); /* terminate the dotted line */
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#endif
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puts ("Done.\n");
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/* XXX - checksum the data? */
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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/* ------------------------------------------------------------------------- */
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static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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int ret_val = FPGA_FAIL; /* assume the worst */
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Xilinx_Spartan3_Slave_Serial_fns *fn = desc->iface_fns;
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int i;
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unsigned char val;
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PRINTF ("%s: start with interface functions @ 0x%p\n",
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__FUNCTION__, fn);
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if (fn) {
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size_t bytecount = 0;
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unsigned char *data = (unsigned char *) buf;
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int cookie = desc->cookie; /* make a local copy */
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unsigned long ts; /* timestamp */
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PRINTF ("%s: Function Table:\n"
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"ptr:\t0x%p\n"
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"struct: 0x%p\n"
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"pgm:\t0x%p\n"
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"init:\t0x%p\n"
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"clk:\t0x%p\n"
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"wr:\t0x%p\n"
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"done:\t0x%p\n\n",
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__FUNCTION__, &fn, fn, fn->pgm, fn->init,
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fn->clk, fn->wr, fn->done);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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printf ("Loading FPGA Device %d...\n", cookie);
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#endif
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/*
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* Run the pre configuration function if there is one.
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*/
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if (*fn->pre) {
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(*fn->pre) (cookie);
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}
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/* Establish the initial state */
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(*fn->pgm) (TRUE, TRUE, cookie); /* Assert the program, commit */
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/* Wait for INIT state (init low) */
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ts = get_timer (0); /* get current time */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for INIT to start.\n");
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return FPGA_FAIL;
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}
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} while (!(*fn->init) (cookie));
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/* Get ready for the burn */
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CONFIG_FPGA_DELAY ();
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(*fn->pgm) (FALSE, TRUE, cookie); /* Deassert the program, commit */
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ts = get_timer (0); /* get current time */
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/* Now wait for INIT to go high */
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do {
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CONFIG_FPGA_DELAY ();
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for INIT to clear.\n");
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return FPGA_FAIL;
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}
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} while ((*fn->init) (cookie));
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/* Load the data */
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if(*fn->bwr)
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(*fn->bwr) (data, bsize, TRUE, cookie);
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else {
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while (bytecount < bsize) {
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/* Xilinx detects an error if INIT goes low (active)
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while DONE is low (inactive) */
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if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
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puts ("** CRC error during FPGA load.\n");
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return (FPGA_FAIL);
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}
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val = data [bytecount ++];
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i = 8;
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do {
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/* Deassert the clock */
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(*fn->clk) (FALSE, TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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/* Write data */
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(*fn->wr) ((val & 0x80), TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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/* Assert the clock */
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(*fn->clk) (TRUE, TRUE, cookie);
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CONFIG_FPGA_DELAY ();
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val <<= 1;
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i --;
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} while (i > 0);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (bytecount % (bsize / 40) == 0)
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putc ('.'); /* let them know we are alive */
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#endif
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}
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}
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CONFIG_FPGA_DELAY ();
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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putc ('\n'); /* terminate the dotted line */
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#endif
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/* now check for done signal */
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ts = get_timer (0); /* get current time */
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ret_val = FPGA_SUCCESS;
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(*fn->wr) (TRUE, TRUE, cookie);
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while (! (*fn->done) (cookie)) {
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/* XXX - we should have a check in here somewhere to
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* make sure we aren't busy forever... */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (FALSE, TRUE, cookie); /* Deassert the clock pin */
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CONFIG_FPGA_DELAY ();
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(*fn->clk) (TRUE, TRUE, cookie); /* Assert the clock pin */
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putc ('*');
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if (get_timer (ts) > CONFIG_SYS_FPGA_WAIT) { /* check the time */
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puts ("** Timeout waiting for DONE to clear.\n");
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ret_val = FPGA_FAIL;
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break;
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}
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}
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putc ('\n'); /* terminate the dotted line */
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/*
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* Run the post configuration function if there is one.
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*/
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if (*fn->post)
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(*fn->post) (cookie);
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#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
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if (ret_val == FPGA_SUCCESS)
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puts ("Done.\n");
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else
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puts ("Fail.\n");
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#endif
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} else {
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printf ("%s: NULL Interface function table!\n", __FUNCTION__);
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}
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return ret_val;
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}
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static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize)
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{
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/* Readback is only available through the Slave Parallel and */
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/* boundary-scan interfaces. */
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printf ("%s: Slave Serial Dumping is unavailable\n",
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__FUNCTION__);
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return FPGA_FAIL;
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}
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