Aneesh V 882f80b993 armv7: stronger barrier for cache-maintenance operations ... set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V <aneesh@ti.com>		2011-09-04 11:36:16 +02:00
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mx5	MX: MX35 / MX5: uniform clock command with powerpc	2011-09-04 11:36:11 +02:00
omap-common	omap: fix gpio related build breaks	2011-09-04 11:33:36 +02:00
omap3	omap: enable caches at system start-up	2011-09-04 11:36:16 +02:00
omap4	omap: enable caches at system start-up	2011-09-04 11:36:16 +02:00
s5p-common	Timer: Remove reset_timer() for non-Nios2 arches	2011-07-26 14:53:30 +02:00
s5pc1xx	armv7: adapt s5pc1xx to the new cache maintenance framework	2011-07-04 10:55:25 +02:00
s5pc2xx	S5PC2XX: clock: support pwm clock for evt1 (cpu revision 1)	2011-05-26 19:33:25 +09:00
tegra2	Tegra2: Use clock and pinmux functions to simplify code	2011-09-04 11:36:15 +02:00
u8500	Timer: Remove set_timer completely	2011-07-26 14:52:17 +02:00
cache_v7.c	armv7: stronger barrier for cache-maintenance operations	2011-09-04 11:36:16 +02:00
config.mk	ARM: Rename arch/arm/cpu/arm_cortexa8 to armv7	2010-07-05 19:59:55 -04:00
cpu.c	omap: add MMC and FAT support to SPL	2011-08-03 12:49:20 +02:00
Makefile	omap: add basic SPL support	2011-08-03 12:49:20 +02:00
start.S	omap: add MMC and FAT support to SPL	2011-08-03 12:49:20 +02:00
syslib.c	ARMV7: Vexpress: fix build errors	2010-12-08 23:44:21 +01:00
u-boot.lds	armv7: start.S: fixes and enhancements for SPL	2011-08-03 12:49:20 +02:00