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c994d3d203
VDD SOC normal run changed to 0.85V LPDDR4 freq0 change from 4000MTS to 2400MTS Signed-off-by: haidong.zheng <haidong.zheng@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
48 lines
1.1 KiB
Plaintext
48 lines
1.1 KiB
Plaintext
menu "i.MX8M DDR controllers"
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depends on ARCH_IMX8M
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config IMX8M_DRAM
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bool "imx8m dram"
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config IMX8M_LPDDR4
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bool "imx8m lpddr4"
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select IMX8M_DRAM
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help
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Select the i.MX8M LPDDR4 driver support on i.MX8M SOC.
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config IMX8M_DDR4
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bool "imx8m ddr4"
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select IMX8M_DRAM
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help
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Select the i.MX8M DDR4 driver support on i.MX8M SOC.
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config IMX8M_DDR3L
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bool "imx8m ddr3l"
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select IMX8M_DRAM
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help
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Select the i.MX8M DDR3L driver support on i.MX8M SOC.
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config SAVED_DRAM_TIMING_BASE
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hex "Define the base address for saved dram timing"
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help
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after DRAM is trained, need to save the dram related timming
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info into memory for low power use. OCRAM_S is used for this
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purpose on i.MX8MM.
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default 0x180000
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config IMX8M_DRAM_INLINE_ECC
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bool "imx8mp inline ECC"
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depends on IMX8MP && IMX8M_LPDDR4
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help
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Select this config if you want to use inline ecc feature for
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imx8mp-evk board.
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config IMX8M_VDD_SOC_850MV
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bool "imx8mp change the vdd_soc voltage to 850mv"
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depends on IMX8MP
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config IMX8M_LPDDR4_FREQ0_2400MTS
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bool "imx8m PDDR4 freq0 change from 4000MTS to 2400MTS"
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endmenu
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