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https://github.com/brain-hackers/u-boot-brain
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393cb36199
As per new naming convention for Samsung SoC's, all Cortex-A9 and Cortex-A15 based SoC's will be classified under the name Exynos. Cortex-A9 and Cortex-A15 based SoC's will be sub-classified as Exynos4 and Exynos5 respectively. In order to better adapt and reuse code across various upcoming Samsung Exynos based boards, all uses of s5pc210 prefix/suffix/directory-names are renamed in this patch. s5pc210 is renamed as exynos4210 and S5PC210/s5pc210 suffix/prefix are renamed as exynos4/EXYNOS4. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
52 lines
1.9 KiB
C
52 lines
1.9 KiB
C
/*
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* (C) Copyright 2010 Samsung Electronics
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* Naveen Krishna Ch <ch.naveen@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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* Note: This file contains the register description for SROMC
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*
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*/
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#ifndef __ASM_ARCH_SROMC_H_
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#define __ASM_ARCH_SROMC_H_
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#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0))
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#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/
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/* 1-> Byte base address*/
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#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2))
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#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3))
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#define SROMC_BC_TACS(x) (x << 28) /* address set-up */
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#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */
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#define SROMC_BC_TACC(x) (x << 16) /* access cycle */
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#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */
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#define SROMC_BC_TAH(x) (x << 8) /* address holding time */
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#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */
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#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */
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#ifndef __ASSEMBLY__
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struct s5p_sromc {
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unsigned int bw;
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unsigned int bc[4];
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};
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#endif /* __ASSEMBLY__ */
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/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
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void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf);
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#endif /* __ASM_ARCH_SROMC_H_ */
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