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https://github.com/brain-hackers/u-boot-brain
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822593f028
Now proper GPIO parts numbering is handled at Samsung devices. This fix is necessary for code using GPIO located at other banks than first. Test HW: - Exynos4210 - Trats - S5PC110 - goni Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
250 lines
6.8 KiB
C
250 lines
6.8 KiB
C
/*
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* (C) Copyright 2010 Samsung Electronics
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* Minkyu Kang <mk7.kang@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef __ASM_ARCH_GPIO_H
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#define __ASM_ARCH_GPIO_H
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#ifndef __ASSEMBLY__
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struct s5p_gpio_bank {
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unsigned int con;
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unsigned int dat;
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unsigned int pull;
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unsigned int drv;
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unsigned int pdn_con;
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unsigned int pdn_pull;
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unsigned char res1[8];
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};
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struct exynos4_gpio_part1 {
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struct s5p_gpio_bank a0;
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struct s5p_gpio_bank a1;
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struct s5p_gpio_bank b;
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struct s5p_gpio_bank c0;
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struct s5p_gpio_bank c1;
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struct s5p_gpio_bank d0;
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struct s5p_gpio_bank d1;
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struct s5p_gpio_bank e0;
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struct s5p_gpio_bank e1;
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struct s5p_gpio_bank e2;
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struct s5p_gpio_bank e3;
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struct s5p_gpio_bank e4;
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struct s5p_gpio_bank f0;
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struct s5p_gpio_bank f1;
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struct s5p_gpio_bank f2;
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struct s5p_gpio_bank f3;
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};
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struct exynos4_gpio_part2 {
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struct s5p_gpio_bank j0;
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struct s5p_gpio_bank j1;
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struct s5p_gpio_bank k0;
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struct s5p_gpio_bank k1;
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struct s5p_gpio_bank k2;
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struct s5p_gpio_bank k3;
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struct s5p_gpio_bank l0;
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struct s5p_gpio_bank l1;
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struct s5p_gpio_bank l2;
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struct s5p_gpio_bank y0;
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struct s5p_gpio_bank y1;
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struct s5p_gpio_bank y2;
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struct s5p_gpio_bank y3;
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struct s5p_gpio_bank y4;
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struct s5p_gpio_bank y5;
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struct s5p_gpio_bank y6;
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struct s5p_gpio_bank res1[80];
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struct s5p_gpio_bank x0;
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struct s5p_gpio_bank x1;
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struct s5p_gpio_bank x2;
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struct s5p_gpio_bank x3;
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};
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struct exynos4_gpio_part3 {
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struct s5p_gpio_bank z;
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};
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struct exynos5_gpio_part1 {
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struct s5p_gpio_bank a0;
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struct s5p_gpio_bank a1;
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struct s5p_gpio_bank a2;
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struct s5p_gpio_bank b0;
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struct s5p_gpio_bank b1;
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struct s5p_gpio_bank b2;
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struct s5p_gpio_bank b3;
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struct s5p_gpio_bank c0;
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struct s5p_gpio_bank c1;
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struct s5p_gpio_bank c2;
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struct s5p_gpio_bank c3;
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struct s5p_gpio_bank d0;
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struct s5p_gpio_bank d1;
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struct s5p_gpio_bank y0;
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struct s5p_gpio_bank y1;
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struct s5p_gpio_bank y2;
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struct s5p_gpio_bank y3;
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struct s5p_gpio_bank y4;
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struct s5p_gpio_bank y5;
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struct s5p_gpio_bank y6;
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struct s5p_gpio_bank res1[0x3];
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struct s5p_gpio_bank c4;
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struct s5p_gpio_bank res2[0x48];
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struct s5p_gpio_bank x0;
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struct s5p_gpio_bank x1;
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struct s5p_gpio_bank x2;
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struct s5p_gpio_bank x3;
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};
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struct exynos5_gpio_part2 {
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struct s5p_gpio_bank e0;
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struct s5p_gpio_bank e1;
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struct s5p_gpio_bank f0;
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struct s5p_gpio_bank f1;
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struct s5p_gpio_bank g0;
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struct s5p_gpio_bank g1;
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struct s5p_gpio_bank g2;
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struct s5p_gpio_bank h0;
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struct s5p_gpio_bank h1;
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};
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struct exynos5_gpio_part3 {
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struct s5p_gpio_bank v0;
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struct s5p_gpio_bank v1;
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struct s5p_gpio_bank res1[0x1];
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struct s5p_gpio_bank v2;
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struct s5p_gpio_bank v3;
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struct s5p_gpio_bank res2[0x1];
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struct s5p_gpio_bank v4;
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};
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struct exynos5_gpio_part4 {
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struct s5p_gpio_bank z;
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};
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/* functions */
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void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
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void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
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void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
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void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
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unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
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void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
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void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
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void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
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/* GPIO pins per bank */
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#define GPIO_PER_BANK 8
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#define exynos4_gpio_part1_get_nr(bank, pin) \
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((((((unsigned int) &(((struct exynos4_gpio_part1 *) \
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EXYNOS4_GPIO_PART1_BASE)->bank)) \
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- EXYNOS4_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
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* GPIO_PER_BANK) + pin)
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#define EXYNOS4_GPIO_PART1_MAX ((sizeof(struct exynos4_gpio_part1) \
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/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
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#define exynos4_gpio_part2_get_nr(bank, pin) \
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(((((((unsigned int) &(((struct exynos4_gpio_part2 *) \
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EXYNOS4_GPIO_PART2_BASE)->bank)) \
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- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
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* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
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#define exynos5_gpio_part1_get_nr(bank, pin) \
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((((((unsigned int) &(((struct exynos5_gpio_part1 *) \
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EXYNOS5_GPIO_PART1_BASE)->bank)) \
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- EXYNOS5_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
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* GPIO_PER_BANK) + pin)
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#define EXYNOS5_GPIO_PART1_MAX ((sizeof(struct exynos5_gpio_part1) \
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/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
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#define exynos5_gpio_part2_get_nr(bank, pin) \
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(((((((unsigned int) &(((struct exynos5_gpio_part2 *) \
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EXYNOS5_GPIO_PART2_BASE)->bank)) \
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- EXYNOS5_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
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* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART1_MAX)
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#define EXYNOS5_GPIO_PART2_MAX ((sizeof(struct exynos5_gpio_part2) \
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/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
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#define exynos5_gpio_part3_get_nr(bank, pin) \
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(((((((unsigned int) &(((struct exynos5_gpio_part3 *) \
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EXYNOS5_GPIO_PART3_BASE)->bank)) \
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- EXYNOS5_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
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* GPIO_PER_BANK) + pin) + EXYNOS5_GPIO_PART2_MAX)
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static inline unsigned int s5p_gpio_base(int nr)
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{
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if (cpu_is_exynos5()) {
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if (nr < EXYNOS5_GPIO_PART1_MAX)
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return EXYNOS5_GPIO_PART1_BASE;
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else if (nr < EXYNOS5_GPIO_PART2_MAX)
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return EXYNOS5_GPIO_PART2_BASE;
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else
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return EXYNOS5_GPIO_PART3_BASE;
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} else if (cpu_is_exynos4()) {
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if (nr < EXYNOS4_GPIO_PART1_MAX)
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return EXYNOS4_GPIO_PART1_BASE;
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else
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return EXYNOS4_GPIO_PART2_BASE;
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}
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return 0;
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}
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static inline unsigned int s5p_gpio_part_max(int nr)
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{
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if (cpu_is_exynos5()) {
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if (nr < EXYNOS5_GPIO_PART1_MAX)
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return 0;
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else if (nr < EXYNOS5_GPIO_PART2_MAX)
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return EXYNOS5_GPIO_PART1_MAX;
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else
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return EXYNOS5_GPIO_PART2_MAX;
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} else if (cpu_is_exynos4()) {
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if (nr < EXYNOS4_GPIO_PART1_MAX)
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return 0;
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else
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return EXYNOS4_GPIO_PART1_MAX;
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}
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return 0;
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}
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#endif
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/* Pin configurations */
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#define GPIO_INPUT 0x0
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#define GPIO_OUTPUT 0x1
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#define GPIO_IRQ 0xf
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#define GPIO_FUNC(x) (x)
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/* Pull mode */
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#define GPIO_PULL_NONE 0x0
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#define GPIO_PULL_DOWN 0x1
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#define GPIO_PULL_UP 0x3
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/* Drive Strength level */
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#define GPIO_DRV_1X 0x0
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#define GPIO_DRV_3X 0x1
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#define GPIO_DRV_2X 0x2
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#define GPIO_DRV_4X 0x3
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#define GPIO_DRV_FAST 0x0
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#define GPIO_DRV_SLOW 0x1
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#endif
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