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https://github.com/brain-hackers/u-boot-brain
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d2a6982f9b
This patch set supports exynos display port drivers. DisplayPort is an industry standard device to accommodate the increasing board adoption of digital display technology within the PC and consumer electronics. The interface supports internal chip-to-chip and external box-to-box digital display connections. Signed-off-by: Donghwa Lee <dh09.lee@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
215 lines
3.5 KiB
C
215 lines
3.5 KiB
C
/*
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* Copyright (C) 2012 Samsung Electronics
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*
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* Author: Donghwa Lee <dh09.lee@samsung.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#ifndef _DP_INFO_H
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#define _DP_INFO_H
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#define msleep(a) udelay(a * 1000)
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#define DP_TIMEOUT_LOOP_COUNT 100
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#define MAX_CR_LOOP 5
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#define MAX_EQ_LOOP 4
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#define EXYNOS_DP_SUCCESS 0
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enum {
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DP_DISABLE,
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DP_ENABLE,
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};
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struct edp_disp_info {
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char *name;
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unsigned int h_total;
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unsigned int h_res;
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unsigned int h_sync_width;
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unsigned int h_back_porch;
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unsigned int h_front_porch;
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unsigned int v_total;
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unsigned int v_res;
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unsigned int v_sync_width;
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unsigned int v_back_porch;
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unsigned int v_front_porch;
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unsigned int v_sync_rate;
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};
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struct edp_link_train_info {
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unsigned int lt_status;
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unsigned int ep_loop;
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unsigned int cr_loop[4];
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};
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struct edp_video_info {
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unsigned int master_mode;
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unsigned int bist_mode;
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unsigned int bist_pattern;
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unsigned int h_sync_polarity;
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unsigned int v_sync_polarity;
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unsigned int interlaced;
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unsigned int color_space;
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unsigned int dynamic_range;
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unsigned int ycbcr_coeff;
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unsigned int color_depth;
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};
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struct edp_device_info {
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struct edp_disp_info disp_info;
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struct edp_link_train_info lt_info;
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struct edp_video_info video_info;
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/*below info get from panel during training*/
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unsigned char lane_bw;
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unsigned char lane_cnt;
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unsigned char dpcd_rev;
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/*support enhanced frame cap */
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unsigned char dpcd_efc;
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};
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enum analog_power_block {
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AUX_BLOCK,
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CH0_BLOCK,
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CH1_BLOCK,
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CH2_BLOCK,
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CH3_BLOCK,
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ANALOG_TOTAL,
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POWER_ALL
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};
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enum pll_status {
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PLL_UNLOCKED = 0,
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PLL_LOCKED
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};
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enum {
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COLOR_RGB,
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COLOR_YCBCR422,
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COLOR_YCBCR444
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};
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enum {
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VESA,
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CEA
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};
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enum {
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COLOR_YCBCR601,
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COLOR_YCBCR709
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};
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enum {
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COLOR_6,
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COLOR_8,
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COLOR_10,
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COLOR_12
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};
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enum {
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DP_LANE_BW_1_62 = 0x06,
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DP_LANE_BW_2_70 = 0x0a,
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};
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enum {
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DP_LANE_CNT_1 = 1,
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DP_LANE_CNT_2 = 2,
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DP_LANE_CNT_4 = 4,
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};
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enum {
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DP_DPCD_REV_10 = 0x10,
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DP_DPCD_REV_11 = 0x11,
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};
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enum {
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DP_LT_NONE,
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DP_LT_START,
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DP_LT_CR,
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DP_LT_ET,
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DP_LT_FINISHED,
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DP_LT_FAIL,
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};
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enum {
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PRE_EMPHASIS_LEVEL_0,
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PRE_EMPHASIS_LEVEL_1,
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PRE_EMPHASIS_LEVEL_2,
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PRE_EMPHASIS_LEVEL_3,
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};
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enum {
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PRBS7,
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D10_2,
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TRAINING_PTN1,
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TRAINING_PTN2,
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DP_NONE
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};
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enum {
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VOLTAGE_LEVEL_0,
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VOLTAGE_LEVEL_1,
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VOLTAGE_LEVEL_2,
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VOLTAGE_LEVEL_3,
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};
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enum pattern_type {
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NO_PATTERN,
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COLOR_RAMP,
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BALCK_WHITE_V_LINES,
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COLOR_SQUARE,
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INVALID_PATTERN,
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COLORBAR_32,
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COLORBAR_64,
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WHITE_GRAY_BALCKBAR_32,
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WHITE_GRAY_BALCKBAR_64,
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MOBILE_WHITEBAR_32,
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MOBILE_WHITEBAR_64
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};
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enum {
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CALCULATED_M,
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REGISTER_M
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};
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enum {
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VIDEO_TIMING_FROM_CAPTURE,
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VIDEO_TIMING_FROM_REGISTER
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};
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struct exynos_dp_platform_data {
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struct edp_device_info *edp_dev_info;
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void (*phy_enable)(unsigned int);
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};
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#ifdef CONFIG_EXYNOS_DP
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unsigned int exynos_init_dp(void);
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#else
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unsigned int exynos_init_dp(void)
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{
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return 0;
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}
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#endif
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#endif /* _DP_INFO_H */
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