Stefan Roese 7d2a0534a6 x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region ... To allow bigger 64 bit prefetchable PCI regions in Linux, this patch changes the base address and range of the ACPI area passed to Linux. BayTrail can only physically access 36 bit of PCI address space. So just chaning the range without changing the base address won't work here, as 0xf.ffff.ffff is already the maximum address. With this patch, a maximum of 16 GiB of local DDR is supported. This should be enough for all BayTrail boards though. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2018-10-28 21:02:15 +08:00
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cpu	x86: quark: Specify X86_TSC_TIMER_EARLY_FREQ	2018-10-22 17:51:45 +08:00
dts	x86: dts: edison: configure I2C#6 pins	2018-09-17 17:35:52 +08:00
include/asm	x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region	2018-10-28 21:02:15 +08:00
lib	x86: detect unsupported relocation types	2018-10-22 17:51:45 +08:00
config.mk	x86: Ensure no instruction sets of MMX/SSE are generated in 64-bit build	2018-10-22 17:51:45 +08:00
Kconfig	x86: efi: Refactor the directory of EFI app and payload support	2018-06-17 21:16:04 +08:00
Makefile	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00