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![Ard Biesheuvel](/assets/img/avatar_default.png)
Some instructions in the ARM ISA have multiple output registers, such as ldrd/ldp (load pair), where two registers are loaded from memory, but also ldr with indexing, where the memory base register is incremented as well when the value is loaded to the destination register. MMIO emulation under KVM is based on using the architecturally defined syndrome information that is provided when an exception is taken to the hypervisor. This syndrome information describes whether the instruction that triggered the exception is a load or a store, what the faulting address was, and which register was the destination register. This syndrome information can only describe one destination register, and when the trapping instruction is one with multiple outputs, KVM throws an error like kvm [615929]: Data abort outside memslots with no valid syndrome info on the host and kills the QEMU process with the following error: U-Boot 2020.07-rc3-00208-g88bd5b179360-dirty (Jun 06 2020 - 11:59:22 +0200) DRAM: 1 GiB Flash: error: kvm run failed Function not implemented R00=00000001 R01=00000040 R02=7ee0ce20 R03=00000000 R04=7ffd9eec R05=00000004 R06=7ffda3f8 R07=00000055 R08=7ffd9eec R09=7ef0ded0 R10=7ee0ce20 R11=00000000 R12=00000004 R13=7ee0cdf8 R14=00000000 R15=7ff72d08 PSR=200001d3 --C- A svc32 QEMU: Terminated This means that, in order to run U-Boot in QEMU under KVM, we need to avoid such instructions when accessing emulated devices. For the flash in particular, which is a hybrid between a ROM (backed by a read-only KVM memslot) when in array mode, and an emulated MMIO device (when in write mode), we need to take care to only use instructions that KVM can deal with when they trap. So override the flash read accessors that are used when running on QEMU under KVM. Note that the the 64-bit wide read and write accessors have been omitted: they are never used when running under QEMU given that it does not emulate CFI flash that supports it. Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
190 lines
3.5 KiB
C
190 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017 Tuomas Tynkkynen
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <init.h>
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#include <log.h>
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#include <virtio_types.h>
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#include <virtio.h>
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#ifdef CONFIG_ARM64
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#include <asm/armv8/mmu.h>
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static struct mm_region qemu_arm64_mem_map[] = {
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{
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/* Flash */
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Lowmem peripherals */
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.virt = 0x08000000UL,
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.phys = 0x08000000UL,
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.size = 0x38000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* RAM */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 255UL * SZ_1G,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Highmem PCI-E ECAM memory area */
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.virt = 0x4010000000ULL,
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.phys = 0x4010000000ULL,
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.size = 0x10000000,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* Highmem PCI-E MMIO memory area */
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.virt = 0x8000000000ULL,
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.phys = 0x8000000000ULL,
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.size = 0x8000000000ULL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = qemu_arm64_mem_map;
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#endif
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int board_init(void)
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{
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/*
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* Make sure virtio bus is enumerated so that peripherals
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* on the virtio bus can be discovered by their drivers
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*/
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virtio_init();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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int dram_init_banksize(void)
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{
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fdtdec_setup_memory_banksize();
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return 0;
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}
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void *board_fdt_blob_setup(void)
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{
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/* QEMU loads a generated DTB for us at the start of RAM. */
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return (void *)CONFIG_SYS_SDRAM_BASE;
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}
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void enable_caches(void)
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{
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icache_enable();
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dcache_enable();
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}
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#if defined(CONFIG_EFI_RNG_PROTOCOL)
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#include <efi_loader.h>
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#include <efi_rng.h>
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#include <dm/device-internal.h>
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efi_status_t platform_get_rng_device(struct udevice **dev)
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{
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int ret;
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efi_status_t status = EFI_DEVICE_ERROR;
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struct udevice *bus, *devp;
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for (uclass_first_device(UCLASS_VIRTIO, &bus); bus;
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uclass_next_device(&bus)) {
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for (device_find_first_child(bus, &devp); devp;
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device_find_next_child(&devp)) {
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if (device_get_uclass_id(devp) == UCLASS_RNG) {
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*dev = devp;
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status = EFI_SUCCESS;
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break;
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}
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}
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}
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if (status != EFI_SUCCESS) {
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debug("No rng device found\n");
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return EFI_DEVICE_ERROR;
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}
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if (*dev) {
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ret = device_probe(*dev);
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if (ret)
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return EFI_DEVICE_ERROR;
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} else {
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debug("Couldn't get child device\n");
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return EFI_DEVICE_ERROR;
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}
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return EFI_SUCCESS;
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}
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#endif /* CONFIG_EFI_RNG_PROTOCOL */
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#ifdef CONFIG_ARM64
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#define __W "w"
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#else
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#define __W
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#endif
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u8 flash_read8(void *addr)
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{
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u8 ret;
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asm("ldrb %" __W "0, %1" : "=r"(ret) : "m"(*(u8 *)addr));
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return ret;
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}
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u16 flash_read16(void *addr)
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{
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u16 ret;
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asm("ldrh %" __W "0, %1" : "=r"(ret) : "m"(*(u16 *)addr));
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return ret;
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}
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u32 flash_read32(void *addr)
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{
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u32 ret;
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asm("ldr %" __W "0, %1" : "=r"(ret) : "m"(*(u32 *)addr));
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return ret;
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}
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void flash_write8(u8 value, void *addr)
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{
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asm("strb %" __W "1, %0" : "=m"(*(u8 *)addr) : "r"(value));
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}
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void flash_write16(u16 value, void *addr)
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{
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asm("strh %" __W "1, %0" : "=m"(*(u16 *)addr) : "r"(value));
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}
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void flash_write32(u32 value, void *addr)
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{
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asm("str %" __W "1, %0" : "=m"(*(u32 *)addr) : "r"(value));
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}
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