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https://github.com/brain-hackers/u-boot-brain
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877bfe37dc
This patch introduces the support for Keymile's kmp204x reference design. This design is based on Freescale's P2040/P2041 SoC. The peripherals used by this design are: - DDR3 RAM with SPD support - SPI NOR Flash as boot medium - NAND Flash - 2 PCIe busses (hosts 1 and 3) - 3 FMAN Ethernet devices (FMAN1 DTSEC1/2/5) - 3 Local Bus windows, with one dedicated to the QRIO reset/power mgmt FPGA - 2 HW I2C busses - last but not least, the mandatory serial port The board/keymile/kmp204x code is mostly based on Freescale's P2041rdb support and was changed according to our design (that means essentially removing what is not present on the designs and a few adaptations). There is currently only one prototype board that is based on this design and this patch also introduces it. The board is called kmlion1. Signed-off-by: Stefan Bigler <stefan.bigler@keymile.com> Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> kmp204x: update the ENV #define The comments had to be refined as well as the total size Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com> [York Sun: fix ddr.c] Acked-by: York Sun <yorksun@freescale.com>
69 lines
2.0 KiB
C
69 lines
2.0 KiB
C
/*
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* (C) Copyright 2013 Keymile AG
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* Valentin Longchamp <valentin.longchamp@keymile.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/* KMLION1 */
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#if defined(CONFIG_KMLION1)
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#define CONFIG_HOSTNAME kmlion1
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#define CONFIG_KM_BOARD_NAME "kmlion1"
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#else
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#error ("Board not supported")
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#endif
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#define CONFIG_KMP204X
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#include "km/kmp204x-common.h"
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#if defined(CONFIG_KMLION1)
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/* App1 Local bus */
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#define CONFIG_SYS_LBAPP1_BASE 0xD0000000
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#define CONFIG_SYS_LBAPP1_BASE_PHYS 0xFD0000000ull
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#define CONFIG_SYS_LBAPP1_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP1_BASE_PHYS) \
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| BR_PS_8 /* Port Size 8 bits */ \
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| BR_DECC_OFF /* no error corr */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_LBAPP1_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
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| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
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| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
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| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
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| OR_GPCM_TRLX /* relaxed tmgs */ \
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| OR_GPCM_EAD) /* extra bus clk cycles */
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/* Local bus app1 Base Address */
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#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_LBAPP1_BR_PRELIM
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/* Local bus app1 Options */
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#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_LBAPP1_OR_PRELIM
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/* App2 Local bus */
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#define CONFIG_SYS_LBAPP2_BASE 0xE0000000
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#define CONFIG_SYS_LBAPP2_BASE_PHYS 0xFE0000000ull
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#define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
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| BR_PS_8 /* Port Size 8 bits */ \
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| BR_DECC_OFF /* no error corr */ \
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| BR_MS_GPCM /* MSEL = GPCM */ \
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| BR_V) /* valid */
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#define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB /* length 256MB */ \
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| OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
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| OR_GPCM_CSNT /* LCS 1/4 clk before */ \
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| OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
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| OR_GPCM_TRLX /* relaxed tmgs */ \
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| OR_GPCM_EAD) /* extra bus clk cycles */
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/* Local bus app2 Base Address */
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#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_LBAPP2_BR_PRELIM
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/* Local bus app2 Options */
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#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_LBAPP2_OR_PRELIM
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#endif
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#endif /* __CONFIG_H */
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