Paul Burton 8755d50706 MIPS: clear TagLo select 2 during cache init ... Current MIPS cores from Imagination Technologies use TagLo select 2 for the data cache. The architecture requires that it is safe for software to write to this register even if it isn't present, so take the trivial option of clearing both selects 0 & 2. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>		2015-01-29 12:55:01 +01:00
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cpu	MIPS: unify cache initialization code	2015-01-29 12:55:01 +01:00
include/asm	MIPS: avoid .set ISA for cache operations	2015-01-29 12:55:00 +01:00
lib	MIPS: clear TagLo select 2 during cache init	2015-01-29 12:55:01 +01:00
config.mk	MIPS: add .padding section to linker script	2014-11-01 18:18:05 +01:00
Kconfig	MIPS: allow systems to skip loads during cache init	2015-01-29 12:55:01 +01:00
Makefile	MIPS: replace $(CPU) with Kconfig symbols	2015-01-21 14:06:04 +01:00