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![Paul Kocialkowski](/assets/img/avatar_default.png)
Orion5x, Kirkwood and Armada XP platforms come with a single TWSI (I2C) MVTWSI controller. However, other platforms using MVTWSI may come with more: this is the case on Allwinner (sunxi) platforms, where up to 4 controllers can be found on the same chip. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
478 lines
14 KiB
C
478 lines
14 KiB
C
/*
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* Driver for the TWSI (i2c) controller found on the Marvell
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* orion5x and kirkwood SoC families.
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*
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* Author: Albert Aribaud <albert.u.boot@aribaud.net>
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* Copyright (c) 2010 Albert Aribaud.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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/*
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* include a file that will provide CONFIG_I2C_MVTWSI_BASE*
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* and possibly other settings
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*/
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#if defined(CONFIG_ORION5X)
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#include <asm/arch/orion5x.h>
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#elif (defined(CONFIG_KIRKWOOD) || defined(CONFIG_ARMADA_XP))
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#include <asm/arch/soc.h>
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#elif defined(CONFIG_SUNXI)
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#include <asm/arch/i2c.h>
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#else
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#error Driver mvtwsi not supported by SoC or board
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#endif
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/*
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* TWSI register structure
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*/
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#ifdef CONFIG_SUNXI
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struct mvtwsi_registers {
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u32 slave_address;
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u32 xtnd_slave_addr;
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u32 data;
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u32 control;
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u32 status;
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u32 baudrate;
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u32 soft_reset;
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};
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#else
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struct mvtwsi_registers {
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u32 slave_address;
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u32 data;
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u32 control;
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union {
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u32 status; /* when reading */
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u32 baudrate; /* when writing */
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};
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u32 xtnd_slave_addr;
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u32 reserved[2];
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u32 soft_reset;
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};
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#endif
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/*
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* Control register fields
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*/
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#define MVTWSI_CONTROL_ACK 0x00000004
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#define MVTWSI_CONTROL_IFLG 0x00000008
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#define MVTWSI_CONTROL_STOP 0x00000010
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#define MVTWSI_CONTROL_START 0x00000020
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#define MVTWSI_CONTROL_TWSIEN 0x00000040
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#define MVTWSI_CONTROL_INTEN 0x00000080
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/*
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* Status register values -- only those expected in normal master
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* operation on non-10-bit-address devices; whatever status we don't
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* expect in nominal conditions (bus errors, arbitration losses,
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* missing ACKs...) we just pass back to the caller as an error
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* code.
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*/
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#define MVTWSI_STATUS_START 0x08
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#define MVTWSI_STATUS_REPEATED_START 0x10
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#define MVTWSI_STATUS_ADDR_W_ACK 0x18
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#define MVTWSI_STATUS_DATA_W_ACK 0x28
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#define MVTWSI_STATUS_ADDR_R_ACK 0x40
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#define MVTWSI_STATUS_ADDR_R_NAK 0x48
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#define MVTWSI_STATUS_DATA_R_ACK 0x50
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#define MVTWSI_STATUS_DATA_R_NAK 0x58
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#define MVTWSI_STATUS_IDLE 0xF8
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/*
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* MVTWSI controller base
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*/
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static struct mvtwsi_registers *twsi_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#ifdef CONFIG_I2C_MVTWSI_BASE0
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case 0:
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return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE0;
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE1
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case 1:
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return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE1;
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE2
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case 2:
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return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE2;
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE3
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case 3:
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return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE3;
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE4
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case 4:
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return (struct mvtwsi_registers *) CONFIG_I2C_MVTWSI_BASE4;
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#endif
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default:
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printf("Missing mvtwsi controller %d base\n", adap->hwadapnr);
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break;
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}
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return NULL;
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}
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/*
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* Returned statuses are 0 for success and nonzero otherwise.
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* Currently, cmd_i2c and cmd_eeprom do not interpret an error status.
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* Thus to ease debugging, the return status contains some debug info:
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* - bits 31..24 are error class: 1 is timeout, 2 is 'status mismatch'.
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* - bits 23..16 are the last value of the control register.
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* - bits 15..8 are the last value of the status register.
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* - bits 7..0 are the expected value of the status register.
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*/
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#define MVTWSI_ERROR_WRONG_STATUS 0x01
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#define MVTWSI_ERROR_TIMEOUT 0x02
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#define MVTWSI_ERROR(ec, lc, ls, es) (((ec << 24) & 0xFF000000) | \
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((lc << 16) & 0x00FF0000) | ((ls<<8) & 0x0000FF00) | (es & 0xFF))
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/*
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* Wait for IFLG to raise, or return 'timeout'; then if status is as expected,
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* return 0 (ok) or return 'wrong status'.
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*/
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static int twsi_wait(struct i2c_adapter *adap, int expected_status)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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int control, status;
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int timeout = 1000;
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do {
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control = readl(&twsi->control);
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if (control & MVTWSI_CONTROL_IFLG) {
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status = readl(&twsi->status);
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if (status == expected_status)
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return 0;
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else
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return MVTWSI_ERROR(
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MVTWSI_ERROR_WRONG_STATUS,
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control, status, expected_status);
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}
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udelay(10); /* one clock cycle at 100 kHz */
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} while (timeout--);
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status = readl(&twsi->status);
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return MVTWSI_ERROR(
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MVTWSI_ERROR_TIMEOUT, control, status, expected_status);
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}
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/*
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* These flags are ORed to any write to the control register
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* They allow global setting of TWSIEN and ACK.
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* By default none are set.
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* twsi_start() sets TWSIEN (in case the controller was disabled)
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* twsi_recv() sets ACK or resets it depending on expected status.
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*/
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static u8 twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
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/*
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* Assert the START condition, either in a single I2C transaction
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* or inside back-to-back ones (repeated starts).
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*/
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static int twsi_start(struct i2c_adapter *adap, int expected_status)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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/* globally set TWSIEN in case it was not */
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twsi_control_flags |= MVTWSI_CONTROL_TWSIEN;
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/* assert START */
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writel(twsi_control_flags | MVTWSI_CONTROL_START, &twsi->control);
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/* wait for controller to process START */
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return twsi_wait(adap, expected_status);
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}
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/*
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* Send a byte (i2c address or data).
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*/
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static int twsi_send(struct i2c_adapter *adap, u8 byte, int expected_status)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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/* put byte in data register for sending */
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writel(byte, &twsi->data);
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/* clear any pending interrupt -- that'll cause sending */
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writel(twsi_control_flags, &twsi->control);
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/* wait for controller to receive byte and check ACK */
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return twsi_wait(adap, expected_status);
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}
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/*
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* Receive a byte.
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* Global mvtwsi_control_flags variable says if we should ack or nak.
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*/
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static int twsi_recv(struct i2c_adapter *adap, u8 *byte)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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int expected_status, status;
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/* compute expected status based on ACK bit in global control flags */
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if (twsi_control_flags & MVTWSI_CONTROL_ACK)
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expected_status = MVTWSI_STATUS_DATA_R_ACK;
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else
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expected_status = MVTWSI_STATUS_DATA_R_NAK;
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/* acknowledge *previous state* and launch receive */
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writel(twsi_control_flags, &twsi->control);
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/* wait for controller to receive byte and assert ACK or NAK */
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status = twsi_wait(adap, expected_status);
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/* if we did receive expected byte then store it */
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if (status == 0)
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*byte = readl(&twsi->data);
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/* return status */
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return status;
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}
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/*
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* Assert the STOP condition.
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* This is also used to force the bus back in idle (SDA=SCL=1).
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*/
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static int twsi_stop(struct i2c_adapter *adap, int status)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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int control, stop_status;
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int timeout = 1000;
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/* assert STOP */
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control = MVTWSI_CONTROL_TWSIEN | MVTWSI_CONTROL_STOP;
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writel(control, &twsi->control);
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/* wait for IDLE; IFLG won't rise so twsi_wait() is no use. */
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do {
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stop_status = readl(&twsi->status);
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if (stop_status == MVTWSI_STATUS_IDLE)
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break;
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udelay(10); /* one clock cycle at 100 kHz */
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} while (timeout--);
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control = readl(&twsi->control);
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if (stop_status != MVTWSI_STATUS_IDLE)
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if (status == 0)
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status = MVTWSI_ERROR(
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MVTWSI_ERROR_TIMEOUT,
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control, status, MVTWSI_STATUS_IDLE);
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return status;
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}
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static unsigned int twsi_calc_freq(const int n, const int m)
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{
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#ifdef CONFIG_SUNXI
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return CONFIG_SYS_TCLK / (10 * (m + 1) * (1 << n));
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#else
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return CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n));
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#endif
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}
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/*
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* Reset controller.
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* Controller reset also resets the baud rate and slave address, so
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* they must be re-established afterwards.
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*/
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static void twsi_reset(struct i2c_adapter *adap)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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/* ensure controller will be enabled by any twsi*() function */
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twsi_control_flags = MVTWSI_CONTROL_TWSIEN;
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/* reset controller */
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writel(0, &twsi->soft_reset);
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/* wait 2 ms -- this is what the Marvell LSP does */
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udelay(20000);
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}
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/*
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* I2C init called by cmd_i2c when doing 'i2c reset'.
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* Sets baud to the highest possible value not exceeding requested one.
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*/
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static unsigned int twsi_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int requested_speed)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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unsigned int tmp_speed, highest_speed, n, m;
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unsigned int baud = 0x44; /* baudrate at controller reset */
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/* use actual speed to collect progressively higher values */
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highest_speed = 0;
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/* compute m, n setting for highest speed not above requested speed */
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for (n = 0; n < 8; n++) {
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for (m = 0; m < 16; m++) {
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tmp_speed = twsi_calc_freq(n, m);
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if ((tmp_speed <= requested_speed)
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&& (tmp_speed > highest_speed)) {
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highest_speed = tmp_speed;
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baud = (m << 3) | n;
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}
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}
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}
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writel(baud, &twsi->baudrate);
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return 0;
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}
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static void twsi_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
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{
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struct mvtwsi_registers *twsi = twsi_get_base(adap);
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/* reset controller */
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twsi_reset(adap);
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/* set speed */
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twsi_i2c_set_bus_speed(adap, speed);
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/* set slave address even though we don't use it */
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writel(slaveadd, &twsi->slave_address);
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writel(0, &twsi->xtnd_slave_addr);
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/* assert STOP but don't care for the result */
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(void) twsi_stop(adap, 0);
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}
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/*
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* Begin I2C transaction with expected start status, at given address.
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* Common to i2c_probe, i2c_read and i2c_write.
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* Expected address status will derive from direction bit (bit 0) in addr.
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*/
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static int i2c_begin(struct i2c_adapter *adap, int expected_start_status,
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u8 addr)
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{
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int status, expected_addr_status;
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/* compute expected address status from direction bit in addr */
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if (addr & 1) /* reading */
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expected_addr_status = MVTWSI_STATUS_ADDR_R_ACK;
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else /* writing */
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expected_addr_status = MVTWSI_STATUS_ADDR_W_ACK;
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/* assert START */
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status = twsi_start(adap, expected_start_status);
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/* send out the address if the start went well */
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if (status == 0)
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status = twsi_send(adap, addr, expected_addr_status);
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/* return ok or status of first failure to caller */
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return status;
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}
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/*
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* I2C probe called by cmd_i2c when doing 'i2c probe'.
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* Begin read, nak data byte, end.
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*/
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static int twsi_i2c_probe(struct i2c_adapter *adap, uchar chip)
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{
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u8 dummy_byte;
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int status;
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/* begin i2c read */
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status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1) | 1);
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/* dummy read was accepted: receive byte but NAK it. */
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if (status == 0)
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status = twsi_recv(adap, &dummy_byte);
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/* Stop transaction */
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twsi_stop(adap, 0);
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/* return 0 or status of first failure */
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return status;
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}
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/*
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* I2C read called by cmd_i2c when doing 'i2c read' and by cmd_eeprom.c
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* Begin write, send address byte(s), begin read, receive data bytes, end.
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*
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* NOTE: some EEPROMS want a stop right before the second start, while
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* some will choke if it is there. Deciding which we should do is eeprom
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* stuff, not i2c, but at the moment the APIs won't let us put it in
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* cmd_eeprom, so we have to choose here, and for the moment that'll be
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* a repeated start without a preceding stop.
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*/
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static int twsi_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *data, int length)
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{
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int status;
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/* begin i2c write to send the address bytes */
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status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
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/* send addr bytes */
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while ((status == 0) && alen--)
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status = twsi_send(adap, addr >> (8*alen),
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MVTWSI_STATUS_DATA_W_ACK);
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/* begin i2c read to receive eeprom data bytes */
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if (status == 0)
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status = i2c_begin(adap, MVTWSI_STATUS_REPEATED_START,
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(chip << 1) | 1);
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/* prepare ACK if at least one byte must be received */
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if (length > 0)
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twsi_control_flags |= MVTWSI_CONTROL_ACK;
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/* now receive actual bytes */
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while ((status == 0) && length--) {
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/* reset NAK if we if no more to read now */
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if (length == 0)
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twsi_control_flags &= ~MVTWSI_CONTROL_ACK;
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/* read current byte */
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status = twsi_recv(adap, data++);
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}
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/* Stop transaction */
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status = twsi_stop(adap, status);
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/* return 0 or status of first failure */
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return status;
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}
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/*
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* I2C write called by cmd_i2c when doing 'i2c write' and by cmd_eeprom.c
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* Begin write, send address byte(s), send data bytes, end.
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*/
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static int twsi_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen, uchar *data, int length)
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{
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int status;
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/* begin i2c write to send the eeprom adress bytes then data bytes */
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status = i2c_begin(adap, MVTWSI_STATUS_START, (chip << 1));
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/* send addr bytes */
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while ((status == 0) && alen--)
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status = twsi_send(adap, addr >> (8*alen),
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MVTWSI_STATUS_DATA_W_ACK);
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/* send data bytes */
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while ((status == 0) && (length-- > 0))
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status = twsi_send(adap, *(data++), MVTWSI_STATUS_DATA_W_ACK);
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/* Stop transaction */
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status = twsi_stop(adap, status);
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/* return 0 or status of first failure */
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return status;
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}
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#ifdef CONFIG_I2C_MVTWSI_BASE0
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U_BOOT_I2C_ADAP_COMPLETE(twsi0, twsi_i2c_init, twsi_i2c_probe,
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twsi_i2c_read, twsi_i2c_write,
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twsi_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE1
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U_BOOT_I2C_ADAP_COMPLETE(twsi1, twsi_i2c_init, twsi_i2c_probe,
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twsi_i2c_read, twsi_i2c_write,
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twsi_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 1)
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE2
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U_BOOT_I2C_ADAP_COMPLETE(twsi2, twsi_i2c_init, twsi_i2c_probe,
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twsi_i2c_read, twsi_i2c_write,
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twsi_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 2)
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#endif
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#ifdef CONFIG_I2C_MVTWSI_BASE3
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U_BOOT_I2C_ADAP_COMPLETE(twsi3, twsi_i2c_init, twsi_i2c_probe,
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twsi_i2c_read, twsi_i2c_write,
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twsi_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 3)
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|
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#endif
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|
#ifdef CONFIG_I2C_MVTWSI_BASE4
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|
U_BOOT_I2C_ADAP_COMPLETE(twsi4, twsi_i2c_init, twsi_i2c_probe,
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|
twsi_i2c_read, twsi_i2c_write,
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|
twsi_i2c_set_bus_speed,
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|
CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 4)
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|
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#endif
|