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![Simon Glass](/assets/img/avatar_default.png)
Make the driver model I2C API available always, even if driver model is not enabled. This allows for a 'soft' switch-over, where drivers can use the new structures in code which is compiled but not yet used. This makes migration easier in some cases. Fix up the existing drivers which define their own 'struct i2c_msg'. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
731 lines
18 KiB
C
731 lines
18 KiB
C
/*
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* Copyright 2013 Broadcom Corporation.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/arch/sysmap.h>
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#include <asm/kona-common/clk.h>
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#include <i2c.h>
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/* Hardware register offsets and field defintions */
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#define CS_OFFSET 0x00000020
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#define CS_ACK_SHIFT 3
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#define CS_ACK_MASK 0x00000008
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#define CS_ACK_CMD_GEN_START 0x00000000
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#define CS_ACK_CMD_GEN_RESTART 0x00000001
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#define CS_CMD_SHIFT 1
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#define CS_CMD_CMD_NO_ACTION 0x00000000
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#define CS_CMD_CMD_START_RESTART 0x00000001
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#define CS_CMD_CMD_STOP 0x00000002
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#define CS_EN_SHIFT 0
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#define CS_EN_CMD_ENABLE_BSC 0x00000001
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#define TIM_OFFSET 0x00000024
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#define TIM_PRESCALE_SHIFT 6
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#define TIM_P_SHIFT 3
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#define TIM_NO_DIV_SHIFT 2
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#define TIM_DIV_SHIFT 0
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#define DAT_OFFSET 0x00000028
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#define TOUT_OFFSET 0x0000002c
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#define TXFCR_OFFSET 0x0000003c
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#define TXFCR_FIFO_FLUSH_MASK 0x00000080
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#define TXFCR_FIFO_EN_MASK 0x00000040
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#define IER_OFFSET 0x00000044
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#define IER_READ_COMPLETE_INT_MASK 0x00000010
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#define IER_I2C_INT_EN_MASK 0x00000008
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#define IER_FIFO_INT_EN_MASK 0x00000002
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#define IER_NOACK_EN_MASK 0x00000001
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#define ISR_OFFSET 0x00000048
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#define ISR_RESERVED_MASK 0xffffff60
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#define ISR_CMDBUSY_MASK 0x00000080
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#define ISR_READ_COMPLETE_MASK 0x00000010
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#define ISR_SES_DONE_MASK 0x00000008
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#define ISR_ERR_MASK 0x00000004
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#define ISR_TXFIFOEMPTY_MASK 0x00000002
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#define ISR_NOACK_MASK 0x00000001
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#define CLKEN_OFFSET 0x0000004c
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#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
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#define CLKEN_M_SHIFT 4
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#define CLKEN_N_SHIFT 1
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#define CLKEN_CLKEN_MASK 0x00000001
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#define FIFO_STATUS_OFFSET 0x00000054
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#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
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#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
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#define HSTIM_OFFSET 0x00000058
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#define HSTIM_HS_MODE_MASK 0x00008000
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#define HSTIM_HS_HOLD_SHIFT 10
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#define HSTIM_HS_HIGH_PHASE_SHIFT 5
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#define HSTIM_HS_SETUP_SHIFT 0
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#define PADCTL_OFFSET 0x0000005c
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#define PADCTL_PAD_OUT_EN_MASK 0x00000004
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#define RXFCR_OFFSET 0x00000068
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#define RXFCR_NACK_EN_SHIFT 7
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#define RXFCR_READ_COUNT_SHIFT 0
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#define RXFIFORDOUT_OFFSET 0x0000006c
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/* Locally used constants */
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#define MAX_RX_FIFO_SIZE 64U /* bytes */
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#define MAX_TX_FIFO_SIZE 64U /* bytes */
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#define I2C_TIMEOUT 100000 /* usecs */
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#define WAIT_INT_CHK 100 /* usecs */
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#if I2C_TIMEOUT % WAIT_INT_CHK
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#error I2C_TIMEOUT must be a multiple of WAIT_INT_CHK
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#endif
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/* Operations that can be commanded to the controller */
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enum bcm_kona_cmd_t {
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BCM_CMD_NOACTION = 0,
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BCM_CMD_START,
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BCM_CMD_RESTART,
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BCM_CMD_STOP,
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};
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enum bus_speed_index {
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BCM_SPD_100K = 0,
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BCM_SPD_400K,
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BCM_SPD_1MHZ,
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};
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/* Internal divider settings for standard mode, fast mode and fast mode plus */
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struct bus_speed_cfg {
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uint8_t time_m; /* Number of cycles for setup time */
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uint8_t time_n; /* Number of cycles for hold time */
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uint8_t prescale; /* Prescale divider */
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uint8_t time_p; /* Timing coefficient */
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uint8_t no_div; /* Disable clock divider */
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uint8_t time_div; /* Post-prescale divider */
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};
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static const struct bus_speed_cfg std_cfg_table[] = {
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[BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
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[BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
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[BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
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};
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struct bcm_kona_i2c_dev {
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void *base;
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uint speed;
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const struct bus_speed_cfg *std_cfg;
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};
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/* Keep these two defines in sync */
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#define DEF_SPD 100000
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#define DEF_SPD_ENUM BCM_SPD_100K
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#define DEF_DEVICE(num) \
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{(void *)CONFIG_SYS_I2C_BASE##num, DEF_SPD, &std_cfg_table[DEF_SPD_ENUM]}
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static struct bcm_kona_i2c_dev g_i2c_devs[CONFIG_SYS_MAX_I2C_BUS] = {
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#ifdef CONFIG_SYS_I2C_BASE0
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DEF_DEVICE(0),
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#endif
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#ifdef CONFIG_SYS_I2C_BASE1
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DEF_DEVICE(1),
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#endif
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#ifdef CONFIG_SYS_I2C_BASE2
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DEF_DEVICE(2),
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#endif
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#ifdef CONFIG_SYS_I2C_BASE3
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DEF_DEVICE(3),
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#endif
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#ifdef CONFIG_SYS_I2C_BASE4
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DEF_DEVICE(4),
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#endif
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#ifdef CONFIG_SYS_I2C_BASE5
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DEF_DEVICE(5),
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#endif
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};
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#define I2C_M_TEN 0x0010 /* ten bit address */
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#define I2C_M_RD 0x0001 /* read data */
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#define I2C_M_NOSTART 0x4000 /* no restart between msgs */
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struct kona_i2c_msg {
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uint16_t addr;
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uint16_t flags;
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uint16_t len;
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uint8_t *buf;
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};
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static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
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enum bcm_kona_cmd_t cmd)
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{
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debug("%s, %d\n", __func__, cmd);
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switch (cmd) {
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case BCM_CMD_NOACTION:
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writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
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(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
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dev->base + CS_OFFSET);
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break;
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case BCM_CMD_START:
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writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
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(CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
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(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
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dev->base + CS_OFFSET);
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break;
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case BCM_CMD_RESTART:
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writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
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(CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
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(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
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dev->base + CS_OFFSET);
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break;
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case BCM_CMD_STOP:
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writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
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(CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
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dev->base + CS_OFFSET);
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break;
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default:
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printf("Unknown command %d\n", cmd);
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}
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}
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static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
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{
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writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
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dev->base + CLKEN_OFFSET);
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}
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static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
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{
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writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
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dev->base + CLKEN_OFFSET);
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}
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/* Wait until at least one of the mask bit(s) are set */
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static unsigned long wait_for_int_timeout(struct bcm_kona_i2c_dev *dev,
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unsigned long time_left,
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uint32_t mask)
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{
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uint32_t status;
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while (time_left) {
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status = readl(dev->base + ISR_OFFSET);
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if ((status & ~ISR_RESERVED_MASK) == 0) {
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debug("Bogus I2C interrupt 0x%x\n", status);
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continue;
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}
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/* Must flush the TX FIFO when NAK detected */
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if (status & ISR_NOACK_MASK)
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writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
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dev->base + TXFCR_OFFSET);
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writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
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if (status & mask) {
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/* We are done since one of the mask bits are set */
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return time_left;
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}
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udelay(WAIT_INT_CHK);
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time_left -= WAIT_INT_CHK;
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}
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return 0;
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}
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/* Send command to I2C bus */
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static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
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enum bcm_kona_cmd_t cmd)
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{
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int rc = 0;
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unsigned long time_left = I2C_TIMEOUT;
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/* Send the command */
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bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
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/* Wait for transaction to finish or timeout */
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time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
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if (!time_left) {
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printf("controller timed out\n");
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rc = -ETIMEDOUT;
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}
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/* Clear command */
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bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
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return rc;
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}
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/* Read a single RX FIFO worth of data from the i2c bus */
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static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
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uint8_t *buf, unsigned int len,
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unsigned int last_byte_nak)
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{
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unsigned long time_left = I2C_TIMEOUT;
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/* Start the RX FIFO */
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writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
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(len << RXFCR_READ_COUNT_SHIFT), dev->base + RXFCR_OFFSET);
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/* Wait for FIFO read to complete */
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time_left =
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wait_for_int_timeout(dev, time_left, IER_READ_COMPLETE_INT_MASK);
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if (!time_left) {
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printf("RX FIFO time out\n");
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return -EREMOTEIO;
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}
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/* Read data from FIFO */
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for (; len > 0; len--, buf++)
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*buf = readl(dev->base + RXFIFORDOUT_OFFSET);
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return 0;
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}
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/* Read any amount of data using the RX FIFO from the i2c bus */
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static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
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struct kona_i2c_msg *msg)
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{
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unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
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unsigned int last_byte_nak = 0;
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unsigned int bytes_read = 0;
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int rc;
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uint8_t *tmp_buf = msg->buf;
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while (bytes_read < msg->len) {
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if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
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last_byte_nak = 1; /* NAK last byte of transfer */
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bytes_to_read = msg->len - bytes_read;
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}
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rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
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last_byte_nak);
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if (rc < 0)
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return -EREMOTEIO;
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bytes_read += bytes_to_read;
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tmp_buf += bytes_to_read;
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}
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return 0;
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}
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/* Write a single byte of data to the i2c bus */
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static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
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unsigned int nak_expected)
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{
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unsigned long time_left = I2C_TIMEOUT;
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unsigned int nak_received;
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/* Clear pending session done interrupt */
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writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
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/* Send one byte of data */
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writel(data, dev->base + DAT_OFFSET);
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time_left = wait_for_int_timeout(dev, time_left, IER_I2C_INT_EN_MASK);
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if (!time_left) {
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debug("controller timed out\n");
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return -ETIMEDOUT;
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}
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nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
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if (nak_received ^ nak_expected) {
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debug("unexpected NAK/ACK\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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/* Write a single TX FIFO worth of data to the i2c bus */
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static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
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uint8_t *buf, unsigned int len)
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{
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int k;
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unsigned long time_left = I2C_TIMEOUT;
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unsigned int fifo_status;
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/* Write data into FIFO */
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for (k = 0; k < len; k++)
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writel(buf[k], (dev->base + DAT_OFFSET));
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/* Wait for FIFO to empty */
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do {
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time_left =
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wait_for_int_timeout(dev, time_left,
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(IER_FIFO_INT_EN_MASK |
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IER_NOACK_EN_MASK));
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fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
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} while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
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/* Check if there was a NAK */
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if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
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printf("unexpected NAK\n");
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return -EREMOTEIO;
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}
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/* Check if a timeout occured */
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if (!time_left) {
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printf("completion timed out\n");
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return -EREMOTEIO;
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}
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return 0;
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}
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/* Write any amount of data using TX FIFO to the i2c bus */
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static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
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struct kona_i2c_msg *msg)
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{
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unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
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unsigned int bytes_written = 0;
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int rc;
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uint8_t *tmp_buf = msg->buf;
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while (bytes_written < msg->len) {
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if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
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bytes_to_write = msg->len - bytes_written;
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rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
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bytes_to_write);
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if (rc < 0)
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return -EREMOTEIO;
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bytes_written += bytes_to_write;
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tmp_buf += bytes_to_write;
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}
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return 0;
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}
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/* Send i2c address */
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static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
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struct kona_i2c_msg *msg)
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{
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unsigned char addr;
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if (msg->flags & I2C_M_TEN) {
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/* First byte is 11110XX0 where XX is upper 2 bits */
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addr = 0xf0 | ((msg->addr & 0x300) >> 7);
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if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
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return -EREMOTEIO;
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/* Second byte is the remaining 8 bits */
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addr = msg->addr & 0xff;
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if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
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return -EREMOTEIO;
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if (msg->flags & I2C_M_RD) {
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/* For read, send restart command */
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if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
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return -EREMOTEIO;
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/* Then re-send the first byte with the read bit set */
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addr = 0xf0 | ((msg->addr & 0x300) >> 7) | 0x01;
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if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
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return -EREMOTEIO;
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}
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} else {
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addr = msg->addr << 1;
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if (msg->flags & I2C_M_RD)
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addr |= 1;
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if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
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return -EREMOTEIO;
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}
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return 0;
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}
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static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
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{
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writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
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dev->base + CLKEN_OFFSET);
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}
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static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
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{
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writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
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dev->base + HSTIM_OFFSET);
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writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
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(dev->std_cfg->time_p << TIM_P_SHIFT) |
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(dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
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(dev->std_cfg->time_div << TIM_DIV_SHIFT),
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dev->base + TIM_OFFSET);
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|
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writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
|
|
(dev->std_cfg->time_n << CLKEN_N_SHIFT) |
|
|
CLKEN_CLKEN_MASK, dev->base + CLKEN_OFFSET);
|
|
}
|
|
|
|
/* Master transfer function */
|
|
static int bcm_kona_i2c_xfer(struct bcm_kona_i2c_dev *dev,
|
|
struct kona_i2c_msg msgs[], int num)
|
|
{
|
|
struct kona_i2c_msg *pmsg;
|
|
int rc = 0;
|
|
int i;
|
|
|
|
/* Enable pad output */
|
|
writel(0, dev->base + PADCTL_OFFSET);
|
|
|
|
/* Enable internal clocks */
|
|
bcm_kona_i2c_enable_clock(dev);
|
|
|
|
/* Send start command */
|
|
rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
|
|
if (rc < 0) {
|
|
printf("Start command failed rc = %d\n", rc);
|
|
goto xfer_disable_pad;
|
|
}
|
|
|
|
/* Loop through all messages */
|
|
for (i = 0; i < num; i++) {
|
|
pmsg = &msgs[i];
|
|
|
|
/* Send restart for subsequent messages */
|
|
if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
|
|
rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
|
|
if (rc < 0) {
|
|
printf("restart cmd failed rc = %d\n", rc);
|
|
goto xfer_send_stop;
|
|
}
|
|
}
|
|
|
|
/* Send slave address */
|
|
if (!(pmsg->flags & I2C_M_NOSTART)) {
|
|
rc = bcm_kona_i2c_do_addr(dev, pmsg);
|
|
if (rc < 0) {
|
|
debug("NAK from addr %2.2x msg#%d rc = %d\n",
|
|
pmsg->addr, i, rc);
|
|
goto xfer_send_stop;
|
|
}
|
|
}
|
|
|
|
/* Perform data transfer */
|
|
if (pmsg->flags & I2C_M_RD) {
|
|
rc = bcm_kona_i2c_read_fifo(dev, pmsg);
|
|
if (rc < 0) {
|
|
printf("read failure\n");
|
|
goto xfer_send_stop;
|
|
}
|
|
} else {
|
|
rc = bcm_kona_i2c_write_fifo(dev, pmsg);
|
|
if (rc < 0) {
|
|
printf("write failure");
|
|
goto xfer_send_stop;
|
|
}
|
|
}
|
|
}
|
|
|
|
rc = num;
|
|
|
|
xfer_send_stop:
|
|
/* Send a STOP command */
|
|
bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
|
|
|
|
xfer_disable_pad:
|
|
/* Disable pad output */
|
|
writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
|
|
|
|
/* Stop internal clock */
|
|
bcm_kona_i2c_disable_clock(dev);
|
|
|
|
return rc;
|
|
}
|
|
|
|
static uint bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev,
|
|
uint speed)
|
|
{
|
|
switch (speed) {
|
|
case 100000:
|
|
dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
|
|
break;
|
|
case 400000:
|
|
dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
|
|
break;
|
|
case 1000000:
|
|
dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
|
|
break;
|
|
default:
|
|
printf("%d hz bus speed not supported\n", speed);
|
|
return -EINVAL;
|
|
}
|
|
dev->speed = speed;
|
|
return 0;
|
|
}
|
|
|
|
static void bcm_kona_i2c_init(struct bcm_kona_i2c_dev *dev)
|
|
{
|
|
/* Parse bus speed */
|
|
bcm_kona_i2c_assign_bus_speed(dev, dev->speed);
|
|
|
|
/* Enable internal clocks */
|
|
bcm_kona_i2c_enable_clock(dev);
|
|
|
|
/* Configure internal dividers */
|
|
bcm_kona_i2c_config_timing(dev);
|
|
|
|
/* Disable timeout */
|
|
writel(0, dev->base + TOUT_OFFSET);
|
|
|
|
/* Enable autosense */
|
|
bcm_kona_i2c_enable_autosense(dev);
|
|
|
|
/* Enable TX FIFO */
|
|
writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
|
|
dev->base + TXFCR_OFFSET);
|
|
|
|
/* Mask all interrupts */
|
|
writel(0, dev->base + IER_OFFSET);
|
|
|
|
/* Clear all pending interrupts */
|
|
writel(ISR_CMDBUSY_MASK |
|
|
ISR_READ_COMPLETE_MASK |
|
|
ISR_SES_DONE_MASK |
|
|
ISR_ERR_MASK |
|
|
ISR_TXFIFOEMPTY_MASK | ISR_NOACK_MASK, dev->base + ISR_OFFSET);
|
|
|
|
/* Enable the controller but leave it idle */
|
|
bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
|
|
|
|
/* Disable pad output */
|
|
writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
|
|
}
|
|
|
|
/*
|
|
* uboot layer
|
|
*/
|
|
struct bcm_kona_i2c_dev *kona_get_dev(struct i2c_adapter *adap)
|
|
{
|
|
return &g_i2c_devs[adap->hwadapnr];
|
|
}
|
|
|
|
static void kona_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
|
|
{
|
|
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
|
|
|
|
if (clk_bsc_enable(dev->base))
|
|
return;
|
|
|
|
bcm_kona_i2c_init(dev);
|
|
}
|
|
|
|
static int kona_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
|
|
int alen, uchar *buffer, int len)
|
|
{
|
|
/* msg[0] writes the addr, msg[1] reads the data */
|
|
struct kona_i2c_msg msg[2];
|
|
unsigned char msgbuf0[64];
|
|
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
|
|
|
|
msg[0].addr = chip;
|
|
msg[0].flags = 0;
|
|
msg[0].len = 1;
|
|
msg[0].buf = msgbuf0; /* msgbuf0 contains incrementing reg addr */
|
|
|
|
msg[1].addr = chip;
|
|
msg[1].flags = I2C_M_RD;
|
|
/* msg[1].buf dest ptr increments each read */
|
|
|
|
msgbuf0[0] = (unsigned char)addr;
|
|
msg[1].buf = buffer;
|
|
msg[1].len = len;
|
|
if (bcm_kona_i2c_xfer(dev, msg, 2) < 0) {
|
|
/* Sending 2 i2c messages */
|
|
kona_i2c_init(adap, adap->speed, adap->slaveaddr);
|
|
debug("I2C read: I/O error\n");
|
|
return -EIO;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
|
|
int alen, uchar *buffer, int len)
|
|
{
|
|
struct kona_i2c_msg msg[1];
|
|
unsigned char msgbuf0[64];
|
|
unsigned int i;
|
|
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
|
|
|
|
msg[0].addr = chip;
|
|
msg[0].flags = 0;
|
|
msg[0].len = 2; /* addr byte plus data */
|
|
msg[0].buf = msgbuf0;
|
|
|
|
for (i = 0; i < len; i++) {
|
|
msgbuf0[0] = addr++;
|
|
msgbuf0[1] = buffer[i];
|
|
if (bcm_kona_i2c_xfer(dev, msg, 1) < 0) {
|
|
kona_i2c_init(adap, adap->speed, adap->slaveaddr);
|
|
debug("I2C write: I/O error\n");
|
|
return -EIO;
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int kona_i2c_probe(struct i2c_adapter *adap, uchar chip)
|
|
{
|
|
uchar tmp;
|
|
|
|
/*
|
|
* read addr 0x0 of the given chip.
|
|
*/
|
|
return kona_i2c_read(adap, chip, 0x0, 1, &tmp, 1);
|
|
}
|
|
|
|
static uint kona_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed)
|
|
{
|
|
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
|
|
return bcm_kona_i2c_assign_bus_speed(dev, speed);
|
|
}
|
|
|
|
/*
|
|
* Register kona i2c adapters. Keep the order below so
|
|
* that the bus number matches the adapter number.
|
|
*/
|
|
#define DEF_ADAPTER(num) \
|
|
U_BOOT_I2C_ADAP_COMPLETE(kona##num, kona_i2c_init, kona_i2c_probe, \
|
|
kona_i2c_read, kona_i2c_write, \
|
|
kona_i2c_set_bus_speed, DEF_SPD, 0x00, num)
|
|
|
|
#ifdef CONFIG_SYS_I2C_BASE0
|
|
DEF_ADAPTER(0)
|
|
#endif
|
|
#ifdef CONFIG_SYS_I2C_BASE1
|
|
DEF_ADAPTER(1)
|
|
#endif
|
|
#ifdef CONFIG_SYS_I2C_BASE2
|
|
DEF_ADAPTER(2)
|
|
#endif
|
|
#ifdef CONFIG_SYS_I2C_BASE3
|
|
DEF_ADAPTER(3)
|
|
#endif
|
|
#ifdef CONFIG_SYS_I2C_BASE4
|
|
DEF_ADAPTER(4)
|
|
#endif
|
|
#ifdef CONFIG_SYS_I2C_BASE5
|
|
DEF_ADAPTER(5)
|
|
#endif
|