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177ba1f927
Add clock driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
28 lines
962 B
Makefile
28 lines
962 B
Makefile
#
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# (C) Copyright 2000-2003
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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#
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# Copyright (C) 2012 Altera Corporation <www.altera.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += misc.o timer.o reset_manager.o clock_manager.o \
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fpga_manager.o board.o
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obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clock_manager_arria10.o \
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reset_manager_arria10.o
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obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
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# QTS-generated config file wrappers
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obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += scan_manager.o wrap_pll_config.o \
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clock_manager_gen5.o reset_manager_gen5.o \
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misc_gen5.o system_manager_gen5.o
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obj-$(CONFIG_SPL_BUILD) += wrap_iocsr_config.o wrap_pinmux_config.o \
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wrap_sdram_config.o
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CFLAGS_wrap_iocsr_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pinmux_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_pll_config.o += -I$(srctree)/board/$(BOARDDIR)
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CFLAGS_wrap_sdram_config.o += -I$(srctree)/board/$(BOARDDIR)
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