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![Ley Foon Tan](/assets/img/avatar_default.png)
Preparation for Stratix 10 enablement. In ARM64, L2 cache controller is accessed through processor registers. So, add CONFIG_SYS_L2_PL310 switch conditional build in order this file can by shared across other SOCFPGAs. Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
207 lines
4.6 KiB
C
207 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/libfdt.h>
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#include <altera.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <watchdog.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/scan_manager.h>
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#include <asm/arch/system_manager.h>
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#include <asm/arch/nic301.h>
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#include <asm/arch/scu.h>
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#include <asm/pl310.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_SYS_L2_PL310
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static const struct pl310_regs *const pl310 =
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(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
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#endif
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struct bsel bsel_str[] = {
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{ "rsvd", "Reserved", },
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{ "fpga", "FPGA (HPS2FPGA Bridge)", },
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{ "nand", "NAND Flash (1.8V)", },
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{ "nand", "NAND Flash (3.0V)", },
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{ "sd", "SD/MMC External Transceiver (1.8V)", },
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{ "sd", "SD/MMC Internal Transceiver (3.0V)", },
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{ "qspi", "QSPI Flash (1.8V)", },
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{ "qspi", "QSPI Flash (3.0V)", },
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};
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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return 0;
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}
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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#ifdef CONFIG_SYS_L2_PL310
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void v7_outer_cache_enable(void)
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{
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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/* enable BRESP, instruction and data prefetch, full line of zeroes */
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setbits_le32(&pl310->pl310_aux_ctrl,
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L310_AUX_CTRL_DATA_PREFETCH_MASK |
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L310_AUX_CTRL_INST_PREFETCH_MASK |
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L310_SHARED_ATT_OVERRIDE_ENABLE);
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/* Enable the L2 cache */
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setbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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void v7_outer_cache_disable(void)
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{
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/* Disable the L2 cache */
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clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
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}
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#endif
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#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
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defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
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int overwrite_console(void)
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{
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return 0;
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}
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#endif
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#ifdef CONFIG_FPGA
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/*
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* FPGA programming support for SoC FPGA Cyclone V
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Altera_SoCFPGA,
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/* Interface type */
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fast_passive_parallel,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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/* add device descriptor to FPGA device table */
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void socfpga_fpga_add(void)
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{
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int i;
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fpga_init();
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for (i = 0; i < ARRAY_SIZE(altera_fpga); i++)
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fpga_add(fpga_altera, &altera_fpga[i]);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_HW_WATCHDOG
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/*
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* In case the watchdog is enabled, make sure to (re-)configure it
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* so that the defined timeout is valid. Otherwise the SPL (Perloader)
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* timeout value is still active which might too short for Linux
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* booting.
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*/
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hw_watchdog_init();
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#else
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/*
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* If the HW watchdog is NOT enabled, make sure it is not running,
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* for example because it was enabled in the preloader. This might
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* trigger a watchdog-triggered reboot of Linux kernel later.
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* Toggle watchdog reset, so watchdog in not running state.
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*/
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
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socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
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#endif
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return 0;
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}
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#ifdef CONFIG_ETH_DESIGNWARE
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static int dwmac_phymode_to_modereg(const char *phymode, u32 *modereg)
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{
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if (!phymode)
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return -EINVAL;
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if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii")) {
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*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
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return 0;
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}
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if (!strcmp(phymode, "rgmii")) {
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*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
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return 0;
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}
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if (!strcmp(phymode, "rmii")) {
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*modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
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return 0;
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}
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return -EINVAL;
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}
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int socfpga_eth_reset_common(void (*resetfn)(const u8 of_reset_id,
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const u8 phymode))
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{
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const void *fdt = gd->fdt_blob;
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struct fdtdec_phandle_args args;
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const char *phy_mode;
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u32 phy_modereg;
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int nodes[2]; /* Max. two GMACs */
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int ret, count;
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int i, node;
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count = fdtdec_find_aliases_for_id(fdt, "ethernet",
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COMPAT_ALTERA_SOCFPGA_DWMAC,
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nodes, ARRAY_SIZE(nodes));
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for (i = 0; i < count; i++) {
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node = nodes[i];
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if (node <= 0)
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continue;
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ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
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"#reset-cells", 1, 0,
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&args);
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if (ret || (args.args_count != 1)) {
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debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
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continue;
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}
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phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
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ret = dwmac_phymode_to_modereg(phy_mode, &phy_modereg);
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if (ret) {
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debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
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continue;
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}
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resetfn(args.args[0], phy_modereg);
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}
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return 0;
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}
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#endif
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