mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![wdenk](/assets/img/avatar_default.png)
- DDR Ram support for PM520 (MPC5200) - support for different flash types (PM520) - USB / IDE / CF-Card / DiskOnChip support for PM520 - 8 bit boot rom support for PM520/CE520 - Add auto SDRAM module detection for MicroSys CPC45 board (MPC8245) - I2C and RTC support for CPC45 - support of new flash type (28F160C3T) for CPC45
82 lines
1.7 KiB
ArmAsm
82 lines
1.7 KiB
ArmAsm
/*
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* board/mx1ads/memsetup.S
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*
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* (c) Copyright 2004
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* Techware Information Technology, Inc.
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* http://www.techware.com.tw/
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*
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* Ming-Len Wu <minglen_wu@techware.com.tw>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#define SDCTL0 0x221000
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#define SDCTL1 0x221004
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_TEXT_BASE:
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.word TEXT_BASE
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.globl memsetup
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memsetup:
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/* memory controller init */
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ldr r1, =SDCTL0
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/* Set Precharge Command */
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ldr r3, =0x92120200
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/* ldr r3, =0x92120251
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*/
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str r3, [r1]
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/* Issue Precharge All Commad */
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ldr r3, =0x8200000
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ldr r2, [r3]
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/* Set AutoRefresh Command */
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ldr r3, =0xA2120200
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str r3, [r1]
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/* Issue AutoRefresh Command */
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ldr r3, =0x8000000
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ldr r2, [r3]
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ldr r2, [r3]
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ldr r2, [r3]
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ldr r2, [r3]
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ldr r2, [r3]
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ldr r2, [r3]
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ldr r2, [r3]
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ldr r2, [r3]
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/* Set Mode Register */
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ldr r3, =0xB2120200
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str r3, [r1]
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/* Issue Mode Register Command */
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ldr r3, =0x08111800 /* Mode Register Value */
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ldr r2, [r3]
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/* Set Normal Mode */
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ldr r3, =0x82124200
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str r3, [r1]
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/* everything is fine now */
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mov pc, lr
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