mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
86cf1c8285
We have the following cases: - CONFIG_NR_DRAM_BANKS was defined, migrate normally - CONFIG_NR_DRAM_BANKS_MAX was defined and then used for CONFIG_NR_DRAM_BANKS after a check, just migrate it over now. - CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 + 2), set this to 8. Signed-off-by: Tom Rini <trini@konsulko.com>
43 lines
1.0 KiB
C
43 lines
1.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014 Samsung Electronics
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*
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* Configuration settings for the SAMSUNG/GOOGLE PEACH-PI board.
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*/
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#ifndef __CONFIG_PEACH_PI_H
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#define __CONFIG_PEACH_PI_H
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"kernel_addr_r=0x22000000\0" \
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"fdt_addr_r=0x23000000\0" \
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"ramdisk_addr_r=0x23300000\0" \
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"scriptaddr=0x30000000\0" \
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"pxefile_addr_r=0x31000000\0"
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#include <configs/exynos5420-common.h>
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#include <configs/exynos5-dt-common.h>
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#include <configs/exynos5-common.h>
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_IRAM_TOP - 0x800)
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/* select serial console configuration */
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#define CONFIG_SERIAL3 /* use SERIAL 3 */
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#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
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/* Display */
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#ifdef CONFIG_LCD
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#define CONFIG_EXYNOS_FB
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#define CONFIG_EXYNOS_DP
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#define LCD_BPP LCD_COLOR16
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#endif
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#define CONFIG_POWER_TPS65090_EC
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/* DRAM Memory Banks */
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#define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */
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#endif /* __CONFIG_PEACH_PI_H */
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