mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
86cf1c8285
We have the following cases: - CONFIG_NR_DRAM_BANKS was defined, migrate normally - CONFIG_NR_DRAM_BANKS_MAX was defined and then used for CONFIG_NR_DRAM_BANKS after a check, just migrate it over now. - CONFIG_NR_DRAM_BANKS was very oddly defined on p2771-0000-* (to 1024 + 2), set this to 8. Signed-off-by: Tom Rini <trini@konsulko.com>
100 lines
2.6 KiB
C
100 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) Stefano Babic <sbabic@denx.de>
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*/
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#ifndef __PCM058_CONFIG_H
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#define __PCM058_CONFIG_H
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#ifdef CONFIG_SPL
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#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
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#include "imx6_spl.h"
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#endif
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#include "mx6_common.h"
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/* Thermal */
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#define CONFIG_IMX_THERMAL
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/* Serial */
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#define CONFIG_MXC_UART
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#define CONFIG_MXC_UART_BASE UART2_BASE
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#define CONSOLE_DEV "ttymxc1"
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#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
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/* Early setup */
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (8 * SZ_1M)
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/* Ethernet */
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET_BASE_ADDR
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#define CONFIG_FEC_XCV_TYPE RGMII
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#define CONFIG_ETHPRIME "FEC"
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#define CONFIG_FEC_MXC_PHYADDR 3
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/* SPI Flash */
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#define CONFIG_SF_DEFAULT_BUS 0
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#define CONFIG_SF_DEFAULT_CS 0
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#define CONFIG_SF_DEFAULT_SPEED 20000000
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#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_SPEED 100000
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#ifndef CONFIG_SPL_BUILD
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/* Enable NAND support */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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#endif
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/* DMA stuff, needed for GPMI/MXS NAND support */
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/* Filesystem support */
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* MMC Configs */
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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#define CONFIG_SYS_FSL_USDHC_NUM 1
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/* Environment organization */
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#define CONFIG_ENV_SIZE (16 * 1024)
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#define CONFIG_ENV_OFFSET (1024 * SZ_1K)
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#define CONFIG_ENV_SECT_SIZE (64 * SZ_1K)
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#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
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#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
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#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
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#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
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#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
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#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
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CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
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#ifdef CONFIG_ENV_IS_IN_NAND
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#define CONFIG_ENV_OFFSET (0x1E0000)
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#define CONFIG_ENV_SECT_SIZE (128 * SZ_1K)
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#endif
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#endif
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