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![Simon Glass](/assets/img/avatar_default.png)
Add a convenience function for any Exynos 542x chip. Signed-off-by: Simon Glass <sjg@chromium.org>
262 lines
5.8 KiB
C
262 lines
5.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2012 Samsung Electronics
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* Donghwa Lee <dh09.lee@samsung.com>
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/power.h>
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static void exynos4_mipi_phy_control(unsigned int dev_index,
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unsigned int enable)
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{
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struct exynos4_power *pmu =
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(struct exynos4_power *)samsung_get_base_power();
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unsigned int addr, cfg = 0;
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if (dev_index == 0)
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addr = (unsigned int)&pmu->mipi_phy0_control;
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else
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addr = (unsigned int)&pmu->mipi_phy1_control;
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cfg = readl(addr);
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if (enable)
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cfg |= (EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
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else
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cfg &= ~(EXYNOS_MIPI_PHY_MRESETN | EXYNOS_MIPI_PHY_ENABLE);
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writel(cfg, addr);
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}
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void set_mipi_phy_ctrl(unsigned int dev_index, unsigned int enable)
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{
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if (cpu_is_exynos4())
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exynos4_mipi_phy_control(dev_index, enable);
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}
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void exynos5_set_usbhost_phy_ctrl(unsigned int enable)
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{
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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if (enable) {
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/* Enabling USBHOST_PHY */
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setbits_le32(&power->usbhost_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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} else {
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/* Disabling USBHOST_PHY */
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clrbits_le32(&power->usbhost_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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}
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}
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void exynos4412_set_usbhost_phy_ctrl(unsigned int enable)
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{
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struct exynos4412_power *power =
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(struct exynos4412_power *)samsung_get_base_power();
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if (enable) {
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/* Enabling USBHOST_PHY */
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setbits_le32(&power->usbhost_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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setbits_le32(&power->hsic1_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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setbits_le32(&power->hsic2_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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} else {
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/* Disabling USBHOST_PHY */
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clrbits_le32(&power->usbhost_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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clrbits_le32(&power->hsic1_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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clrbits_le32(&power->hsic2_phy_control,
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POWER_USB_HOST_PHY_CTRL_EN);
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}
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}
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void set_usbhost_phy_ctrl(unsigned int enable)
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{
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if (cpu_is_exynos5())
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exynos5_set_usbhost_phy_ctrl(enable);
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else if (cpu_is_exynos4())
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if (proid_is_exynos4412())
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exynos4412_set_usbhost_phy_ctrl(enable);
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}
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static void exynos5_set_usbdrd_phy_ctrl(unsigned int enable)
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{
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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if (enable) {
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/* Enabling USBDRD_PHY */
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setbits_le32(&power->usbdrd_phy_control,
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POWER_USB_DRD_PHY_CTRL_EN);
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} else {
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/* Disabling USBDRD_PHY */
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clrbits_le32(&power->usbdrd_phy_control,
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POWER_USB_DRD_PHY_CTRL_EN);
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}
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}
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static void exynos5420_set_usbdev_phy_ctrl(unsigned int enable)
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{
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struct exynos5420_power *power =
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(struct exynos5420_power *)samsung_get_base_power();
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if (enable) {
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/* Enabling USBDEV_PHY */
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setbits_le32(&power->usbdev_phy_control,
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POWER_USB_DRD_PHY_CTRL_EN);
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setbits_le32(&power->usbdev1_phy_control,
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POWER_USB_DRD_PHY_CTRL_EN);
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} else {
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/* Disabling USBDEV_PHY */
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clrbits_le32(&power->usbdev_phy_control,
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POWER_USB_DRD_PHY_CTRL_EN);
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clrbits_le32(&power->usbdev1_phy_control,
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POWER_USB_DRD_PHY_CTRL_EN);
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}
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}
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void set_usbdrd_phy_ctrl(unsigned int enable)
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{
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if (cpu_is_exynos5()) {
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if (proid_is_exynos542x())
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exynos5420_set_usbdev_phy_ctrl(enable);
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else
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exynos5_set_usbdrd_phy_ctrl(enable);
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}
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}
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static void exynos5_dp_phy_control(unsigned int enable)
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{
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unsigned int cfg;
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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cfg = readl(&power->dptx_phy_control);
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if (enable)
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cfg |= EXYNOS_DP_PHY_ENABLE;
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else
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cfg &= ~EXYNOS_DP_PHY_ENABLE;
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writel(cfg, &power->dptx_phy_control);
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}
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void exynos_dp_phy_ctrl(unsigned int enable)
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{
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if (cpu_is_exynos5())
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exynos5_dp_phy_control(enable);
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}
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static void exynos5_set_ps_hold_ctrl(void)
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{
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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/* Set PS-Hold high */
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setbits_le32(&power->ps_hold_control,
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EXYNOS_PS_HOLD_CONTROL_DATA_HIGH);
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}
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/*
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* Set ps_hold data driving value high
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* This enables the machine to stay powered on
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* after the initial power-on condition goes away
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* (e.g. power button).
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*/
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void set_ps_hold_ctrl(void)
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{
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if (cpu_is_exynos5())
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exynos5_set_ps_hold_ctrl();
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}
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static void exynos5_set_xclkout(void)
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{
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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/* use xxti for xclk out */
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clrsetbits_le32(&power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK,
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PMU_DEBUG_XXTI);
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}
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void set_xclkout(void)
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{
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if (cpu_is_exynos5())
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exynos5_set_xclkout();
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}
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/* Enables hardware tripping to power off the system when TMU fails */
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void set_hw_thermal_trip(void)
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{
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if (cpu_is_exynos5()) {
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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/* PS_HOLD_CONTROL register ENABLE_HW_TRIP bit*/
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setbits_le32(&power->ps_hold_control, POWER_ENABLE_HW_TRIP);
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}
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}
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static uint32_t exynos5_get_reset_status(void)
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{
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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return power->inform1;
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}
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static uint32_t exynos4_get_reset_status(void)
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{
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struct exynos4_power *power =
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(struct exynos4_power *)samsung_get_base_power();
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return power->inform1;
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}
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uint32_t get_reset_status(void)
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{
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if (cpu_is_exynos5())
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return exynos5_get_reset_status();
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else
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return exynos4_get_reset_status();
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}
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static void exynos5_power_exit_wakeup(void)
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{
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struct exynos5_power *power =
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(struct exynos5_power *)samsung_get_base_power();
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typedef void (*resume_func)(void);
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((resume_func)power->inform0)();
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}
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static void exynos4_power_exit_wakeup(void)
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{
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struct exynos4_power *power =
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(struct exynos4_power *)samsung_get_base_power();
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typedef void (*resume_func)(void);
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((resume_func)power->inform0)();
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}
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void power_exit_wakeup(void)
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{
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if (cpu_is_exynos5())
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exynos5_power_exit_wakeup();
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else
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exynos4_power_exit_wakeup();
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}
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unsigned int get_boot_mode(void)
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{
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unsigned int om_pin = samsung_get_base_power();
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return readl(om_pin) & OM_PIN_MASK;
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}
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