mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 05:36:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
322 lines
7.6 KiB
ArmAsm
322 lines
7.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2007 Michal Simek
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* (C) Copyright 2004 Atmark Techno, Inc.
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*
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* Michal SIMEK <monstr@monstr.eu>
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* Yasushi SHOJI <yashi@atmark-techno.com>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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.text
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.global _start
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_start:
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/*
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* reserve registers:
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* r10: Stores little/big endian offset for vectors
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* r2: Stores imm opcode
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* r3: Stores brai opcode
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*/
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mts rmsr, r0 /* disable cache */
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addi r8, r0, __end
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mts rslr, r8
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/* TODO: Redo this code to call board_init_f_*() */
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#if defined(CONFIG_SPL_BUILD)
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addi r1, r0, CONFIG_SPL_STACK_ADDR
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mts rshr, r1
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addi r1, r1, -4 /* Decrement SP to top of memory */
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#else
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET - CONFIG_VAL(SYS_MALLOC_F_LEN)
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#else
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addi r1, r0, CONFIG_SYS_INIT_SP_OFFSET
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#endif
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mts rshr, r1
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addi r1, r1, -4 /* Decrement SP to top of memory */
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/* Find-out if u-boot is running on BIG/LITTLE endian platform
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* There are some steps which is necessary to keep in mind:
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* 1. Setup offset value to r6
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* 2. Store word offset value to address 0x0
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* 3. Load just byte from address 0x0
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* 4a) LITTLE endian - r10 contains 0x2 because it is the smallest
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* value that's why is on address 0x0
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* 4b) BIG endian - r10 contains 0x0 because 0x2 offset is on addr 0x3
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*/
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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lwi r7, r0, 0x28
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swi r6, r0, 0x28 /* used first unused MB vector */
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lbui r10, r0, 0x28 /* used first unused MB vector */
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swi r7, r0, 0x28
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/* add opcode instruction for 32bit jump - 2 instruction imm & brai */
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addi r2, r0, 0xb0000000 /* hex b000 opcode imm */
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addi r3, r0, 0xb8080000 /* hew b808 opcode brai */
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#ifdef CONFIG_SYS_RESET_ADDRESS
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/* reset address */
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swi r2, r0, 0x0 /* reset address - imm opcode */
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swi r3, r0, 0x4 /* reset address - brai opcode */
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addik r6, r0, CONFIG_SYS_RESET_ADDRESS
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x2
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sh r7, r0, r8
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rsubi r8, r10, 0x6
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sh r6, r0, r8
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#endif
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#ifdef CONFIG_SYS_USR_EXCEP
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/* user_vector_exception */
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swi r2, r0, 0x8 /* user vector exception - imm opcode */
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swi r3, r0, 0xC /* user vector exception - brai opcode */
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addik r6, r0, _exception_handler
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sw r6, r1, r0
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/*
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* BIG ENDIAN memory map for user exception
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* 0x8: 0xB000XXXX
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* 0xC: 0xB808XXXX
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*
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* then it is necessary to count address for storing the most significant
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* 16bits from _exception_handler address and copy it to
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* 0xa address. Big endian use offset in r10=0 that's why is it just
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* 0xa address. The same is done for the least significant 16 bits
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* for 0xe address.
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*
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* LITTLE ENDIAN memory map for user exception
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* 0x8: 0xXXXX00B0
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* 0xC: 0xXXXX08B8
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*
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* Offset is for little endian setup to 0x2. rsubi instruction decrease
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* address value to ensure that points to proper place which is
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* 0x8 for the most significant 16 bits and
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* 0xC for the least significant 16 bits
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*/
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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/* interrupt_handler */
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swi r2, r0, 0x10 /* interrupt - imm opcode */
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swi r3, r0, 0x14 /* interrupt - brai opcode */
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addik r6, r0, _interrupt_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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/* hardware exception */
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swi r2, r0, 0x20 /* hardware exception - imm opcode */
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swi r3, r0, 0x24 /* hardware exception - brai opcode */
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addik r6, r0, _hw_exception_handler
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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#endif /* CONFIG_SPL_BUILD */
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/* Flush cache before enable cache */
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addik r5, r0, 0
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addik r6, r0, XILINX_DCACHE_BYTE_SIZE
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bralid r15, flush_cache
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nop
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/* enable instruction and data cache */
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mfs r12, rmsr
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ori r12, r12, 0x1a0
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mts rmsr, r12
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/* TODO: Redo this code to call board_init_f_*() */
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clear_bss:
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/* clear BSS segments */
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addi r5, r0, __bss_start
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addi r4, r0, __bss_end
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cmp r6, r5, r4
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beqi r6, 3f
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2:
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swi r0, r5, 0 /* write zero to loc */
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addi r5, r5, 4 /* increment to next loc */
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cmp r6, r5, r4 /* check if we have reach the end */
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bnei r6, 2b
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3: /* jumping to board_init */
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#ifdef CONFIG_DEBUG_UART
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bralid r15, debug_uart_init
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nop
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#endif
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#ifndef CONFIG_SPL_BUILD
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or r5, r0, r0 /* flags - empty */
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addi r31, r0, _gd
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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addi r6, r0, CONFIG_SYS_INIT_SP_OFFSET
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swi r6, r31, GD_MALLOC_BASE
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#endif
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brai board_init_f
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#else
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addi r31, r0, _gd
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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addi r6, r0, CONFIG_SPL_STACK_ADDR
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swi r6, r31, GD_MALLOC_BASE
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#endif
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brai board_init_r
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#endif
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1: bri 1b
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.section .bss
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.align 4
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_gd:
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.space GENERATED_GBL_DATA_SIZE
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#ifndef CONFIG_SPL_BUILD
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/*
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* Read 16bit little endian
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*/
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.text
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.global in16
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.ent in16
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.align 2
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in16: lhu r3, r0, r5
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bslli r4, r3, 8
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bsrli r3, r3, 8
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andi r4, r4, 0xffff
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or r3, r3, r4
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rtsd r15, 8
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sext16 r3, r3
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.end in16
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/*
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* Write 16bit little endian
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* first parameter(r5) - address, second(r6) - short value
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*/
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.text
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.global out16
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.ent out16
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.align 2
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out16: bslli r3, r6, 8
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bsrli r6, r6, 8
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andi r3, r3, 0xffff
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or r3, r3, r6
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sh r3, r0, r5
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rtsd r15, 8
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or r0, r0, r0
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.end out16
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/*
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* Relocate u-boot
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*/
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.text
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.global relocate_code
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.ent relocate_code
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.align 2
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relocate_code:
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/*
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* r5 - start_addr_sp
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* r6 - new_gd
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* r7 - reloc_addr
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*/
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addi r1, r5, 0 /* Start to use new SP */
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addi r31, r6, 0 /* Start to use new GD */
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add r23, r0, r7 /* Move reloc addr to r23 */
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/* Relocate text and data - r12 temp value */
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addi r21, r0, _start
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addi r22, r0, __end - 4 /* Include BSS too */
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rsub r6, r21, r22
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or r5, r0, r0
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1: lw r12, r21, r5 /* Load u-boot data */
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sw r12, r23, r5 /* Write zero to loc */
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cmp r12, r5, r6 /* Check if we have reach the end */
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bneid r12, 1b
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addi r5, r5, 4 /* Increment to next loc - relocate code */
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/* R23 points to the base address. */
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add r23, r0, r7 /* Move reloc addr to r23 */
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addi r24, r0, CONFIG_SYS_TEXT_BASE /* Get reloc offset */
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rsub r23, r24, r23 /* keep - this is already here gd->reloc_off */
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addik r6, r0, 0x2 /* BIG/LITTLE endian offset */
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lwi r7, r0, 0x28
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swi r6, r0, 0x28 /* used first unused MB vector */
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lbui r10, r0, 0x28 /* used first unused MB vector */
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swi r7, r0, 0x28
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#ifdef CONFIG_SYS_USR_EXCEP
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addik r6, r0, _exception_handler
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addk r6, r6, r23 /* add offset */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0xa
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sh r7, r0, r8
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rsubi r8, r10, 0xe
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sh r6, r0, r8
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#endif
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addik r6, r0, _hw_exception_handler
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addk r6, r6, r23 /* add offset */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x22
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sh r7, r0, r8
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rsubi r8, r10, 0x26
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sh r6, r0, r8
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addik r6, r0, _interrupt_handler
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addk r6, r6, r23 /* add offset */
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sw r6, r1, r0
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lhu r7, r1, r10
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rsubi r8, r10, 0x12
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sh r7, r0, r8
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rsubi r8, r10, 0x16
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sh r6, r0, r8
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/* Check if GOT exist */
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addik r21, r23, _got_start
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addik r22, r23, _got_end
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cmpu r12, r21, r22
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beqi r12, 2f /* No GOT table - jump over */
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/* Skip last 3 entries plus 1 because of loop boundary below */
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addik r22, r22, -0x10
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/* Relocate the GOT. */
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3: lw r12, r21, r0 /* Load entry */
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addk r12, r12, r23 /* Add reloc offset */
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sw r12, r21, r0 /* Save entry back */
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cmpu r12, r21, r22 /* Check if this cross boundary */
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bneid r12, 3b
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addik r21. r21, 4
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/* Update pointer to GOT */
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mfs r20, rpc
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addik r20, r20, _GLOBAL_OFFSET_TABLE_ + 8
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addk r20, r20, r23
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/* Flush caches to ensure consistency */
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addik r5, r0, 0
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addik r6, r0, XILINX_DCACHE_BYTE_SIZE
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bralid r15, flush_cache
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nop
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2: addi r5, r31, 0 /* gd is initialized in board_r.c */
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addi r6, r0, CONFIG_SYS_TEXT_BASE
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addi r12, r23, board_init_r
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bra r12 /* Jump to relocated code */
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.end relocate_code
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#endif
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