mirror of
https://github.com/brain-hackers/u-boot-brain
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864915561b
It was observed sometimes U-Boot as the coreboot payload fails to boot on QEMU. This is because TSC calibration fails with no valid frequency. This adds default TSC frequency in the device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
46 lines
675 B
Plaintext
46 lines
675 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* Generic coreboot payload device tree for x86 targets
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*/
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/dts-v1/;
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/include/ "skeleton.dtsi"
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/include/ "serial.dtsi"
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/include/ "keyboard.dtsi"
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/include/ "reset.dtsi"
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/include/ "rtc.dtsi"
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/include/ "tsc_timer.dtsi"
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/ {
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model = "coreboot x86 payload";
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compatible = "coreboot,x86-payload";
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aliases {
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serial0 = &serial;
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};
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config {
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silent_console = <0>;
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};
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chosen {
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stdout-path = "/serial";
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};
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tsc-timer {
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clock-frequency = <1000000000>;
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};
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pci {
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compatible = "pci-x86";
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u-boot,dm-pre-reloc;
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};
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coreboot-fb {
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compatible = "coreboot-fb";
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};
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};
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