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https://github.com/brain-hackers/u-boot-brain
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8645071006
The nios2-io.h defines hardware registers and bits of several FPGA IP cores. It could be divided in to the specific drivers, including altera timer, altera sysid, altera uart and altera jtag uart. The altera pio and altera spi drivers use their own hardware definitions. The removal of nios2-io.h will help modularity and maintenance. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
61 lines
1.1 KiB
C
61 lines
1.1 KiB
C
/*
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* (C) Copyright 2004, Psyent Corporation <www.psyent.com>
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* Scott McNutt <smcnutt@psyent.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <nios2.h>
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#include <asm/cache.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined (CONFIG_SYS_NIOS_SYSID_BASE)
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extern void display_sysid (void);
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#endif /* CONFIG_SYS_NIOS_SYSID_BASE */
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#ifdef CONFIG_DISPLAY_CPUINFO
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int print_cpuinfo(void)
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{
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printf ("CPU : Nios-II\n");
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#if !defined(CONFIG_SYS_NIOS_SYSID_BASE)
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printf ("SYSID : <unknown>\n");
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#else
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display_sysid ();
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#endif
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return (0);
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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disable_interrupts();
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/* indirect call to go beyond 256MB limitation of toolchain */
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nios2_callr(CONFIG_SYS_RESET_ADDR);
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return 0;
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}
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int dcache_status(void)
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{
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return 1;
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}
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void dcache_enable(void)
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{
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flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
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}
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void dcache_disable(void)
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{
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flush_dcache(CONFIG_SYS_DCACHE_SIZE, CONFIG_SYS_DCACHELINE_SIZE);
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}
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int arch_cpu_init(void)
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{
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gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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return 0;
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}
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