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https://github.com/brain-hackers/u-boot-brain
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2d934e5703
This setting will be used by more than just ivybridge so make it common. Also rename it to PCIE_ECAM_BASE which is a more descriptive name. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
41 lines
679 B
Plaintext
41 lines
679 B
Plaintext
if TARGET_CHROMEBOOK_LINK
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config SYS_BOARD
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default "chromebook_link"
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config SYS_VENDOR
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default "google"
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config SYS_SOC
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default "ivybridge"
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config SYS_CONFIG_NAME
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default "chromebook_link"
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select X86_RESET_VECTOR
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE
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select SOUTHBRIDGE_INTEL_C216
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select HAVE_ACPI_RESUME
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select MARK_GRAPHICS_MEM_WRCOMB
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select BOARD_ROMSIZE_KB_8192
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config PCIE_ECAM_BASE
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default 0xf0000000
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config EARLY_POST_CROS_EC
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bool "Enable early post to Chrome OS EC"
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default y
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config SYS_CAR_ADDR
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hex
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default 0xff7e0000
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config SYS_CAR_SIZE
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hex
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default 0x20000
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endif
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